107 lines
4.2 KiB
HTML
107 lines
4.2 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XEND
|
||
— Transactional End</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XEND
|
||
— Transactional End</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>NP 0F 01 D5 XEND</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>RTM</td>
|
||
<td>Specifies the end of an RTM code region.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand2</th>
|
||
<th>Operand3</th>
|
||
<th>Operand4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>The instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will rollback all architectural register and memory updates performed during the RTM execution. The logical processor will resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register is updated to reflect RTM abort information.</p>
|
||
<p>Execution of XEND outside a transactional region causes a general-protection exception (#GP). Execution of XEND while in a suspend read address tracking region causes a transactional abort.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="xend">XEND<a class="anchor" href="#xend">
|
||
¶
|
||
</a></h3>
|
||
<pre>IF (RTM_ACTIVE = 0) THEN
|
||
SIGNAL #GP
|
||
ELSE
|
||
IF SUSLDTRK_ACTIVE = 1
|
||
THEN GOTO RTM_ABORT_PROCESSING;
|
||
FI;
|
||
RTM_NEST_COUNT--
|
||
IF (RTM_NEST_COUNT = 0) THEN
|
||
Try to commit transaction
|
||
IF fail to commit transactional execution
|
||
THEN
|
||
GOTO RTM_ABORT_PROCESSING;
|
||
ELSE (* commit success *)
|
||
RTM_ACTIVE := 0
|
||
FI;
|
||
FI;
|
||
FI;
|
||
(* For any RTM abort condition encountered during RTM execution *)
|
||
RTM_ABORT_PROCESSING:
|
||
Restore architectural register state
|
||
Discard memory updates performed in transaction
|
||
Update EAX with status
|
||
RTM_NEST_COUNT := 0
|
||
RTM_ACTIVE := 0
|
||
SUSLDTRK_ACTIVE := 0
|
||
IF 64-bit Mode
|
||
THEN
|
||
RIP := fallbackRIP
|
||
ELSE
|
||
EIP := fallbackEIP
|
||
FI;
|
||
END
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>XEND void _xend( void );
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="2">#UD</td>
|
||
<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.</td></tr>
|
||
<tr>
|
||
<td>If LOCK prefix is used.</td></tr>
|
||
<tr>
|
||
<td>#GP(0)</td>
|
||
<td>If RTM_ACTIVE = 0.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|