104 lines
5.9 KiB
HTML
104 lines
5.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VREDUCESD
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— Perform a Reduction Transformation on a Scalar Float64 Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VREDUCESD
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— Perform a Reduction Transformation on a Scalar Float64 Value</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.66.0F3A.W1 57 VREDUCESD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8/r</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512D Q</td>
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<td>Perform a reduction transformation on a scalar double precision floating-point value in xmm3/m64 by subtracting a number of fraction bits specified by the imm8 field. Also, upper double precision floating-point value (bits[127:64]) from xmm2 are copied to xmm1[127:64]. Stores the result in xmm1 register.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Perform a reduction transformation of the binary encoded double precision floating-point value in the low qword element of the second source operand (the third operand) and store the reduced result in binary floating-point format to the low qword element of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination operand are copied from respective qword elements of the first source operand (the second operand).</p>
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<p>The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-point source value, where M is a unsigned integer specified by imm8[7:4], see <a href='vreducepd.html#fig-5-28'>Figure 5-28</a>. Specifically, the reduction transformation can be expressed as:</p>
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<p>dest = src – (ROUND(2<sup>M</sup>*src))*2<sup>-M</sup>;</p>
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<p>where “Round()” treats “src”, “2<sup>M</sup>”, and their product as binary floating-point numbers with normalized significand and biased exponents.</p>
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<p>The magnitude of the reduced result can be expressed by considering src= 2<sup>p</sup>*man2,</p>
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<p>where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent</p>
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<p>Then if RC = RNE: 0<=|Reduced Result|<=2<sup>p-M-1</sup></p>
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<p>Then if RC ≠ RNE: 0<=|Reduced Result|<2<sup>p-M</sup></p>
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<p>This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.</p>
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<p>The operation is write masked.</p>
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<p>Handling of special case of input values are listed in <a href='vreducepd.html#tbl-5-29'>Table 5-29</a>.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>ReduceArgumentDP(SRC[63:0], imm8[7:0])
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{
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// Check for NaN
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IF (SRC [63:0] = NAN) THEN
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RETURN (Convert SRC[63:0] to QNaN); FI;
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M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
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RC := imm8[1:0];// Round Control for ROUND() operation
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RC source := imm[2];
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SPE := imm[3];// Suppress Precision Exception
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TMP[63:0] := 2<sup>-M</sup> *{ROUND(2<sup>M</sup>*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2<sup>M</sup> as standard binary FP values
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TMP[63:0] := SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controls
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RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
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}
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</pre>
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<h4 id="vreducesd">VREDUCESD<a class="anchor" href="#vreducesd">
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¶
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</a></h4>
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<pre>IF k1[0] or *no writemask*
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THEN DEST[63:0] := ReduceArgumentDP(SRC2[63:0], imm8[7:0])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[63:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[63:0] = 0
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FI;
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FI;
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DEST[127:64] := SRC1[127:64]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)
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</pre>
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<pre>VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)
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</pre>
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<pre>VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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