137 lines
6.5 KiB
HTML
137 lines
6.5 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VRCP28PS
|
||
— Approximation to the Reciprocal of Packed Single Precision Floating-Point ValuesWith Less Than 2^-28 Relative Error</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VRCP28PS
|
||
— Approximation to the Reciprocal of Packed Single Precision Floating-Point ValuesWith Less Than 2^-28 Relative Error</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>EVEX.512.66.0F38.W0 CA /r VRCP28PS zmm1 {k1}{z}, zmm2/m512/m32bcst {sae}</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512ER</td>
|
||
<td>Computes the approximate reciprocals ( < 2^-28 relative error) of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4</th>
|
||
<th></th>
|
||
<th></th>
|
||
<th></th>
|
||
<th></th>
|
||
<th></th></tr>
|
||
<tr>
|
||
<td>A Full ModRM:reg (w) ModRM:r/m (r) N/A N/A</td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td></tr></table>
|
||
<h3 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h3>
|
||
<p>Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store the results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to < 2^-23 relative error before written to the destination.</p>
|
||
<p>Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.</p>
|
||
<p>If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is ±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.</p>
|
||
<p>The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
|
||
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
|
||
<h3 id="a-numerically-exact-implementation-of-vrcp28xx-can-be-found-at-https---software-intel-com-en-us-articles-refer-">A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-<a class="anchor" href="#a-numerically-exact-implementation-of-vrcp28xx-can-be-found-at-https---software-intel-com-en-us-articles-refer-">
|
||
¶
|
||
</a></h3>
|
||
<h3 id="ence-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2-">ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.<a class="anchor" href="#ence-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2-">
|
||
¶
|
||
</a></h3>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="vrcp28ps--evex-encoded-versions-">VRCP28PS (EVEX Encoded Versions)<a class="anchor" href="#vrcp28ps--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask* THEN
|
||
IF (EVEX.b = 1) AND (SRC *is memory*)
|
||
THEN DEST[i+31:i] := RCP_28_SP(1.0/SRC[31:0]);
|
||
ELSE DEST[i+31:i] := RCP_28_SP(1.0/SRC[i+31:i]);
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI;
|
||
FI;
|
||
ENDFOR;
|
||
</pre>
|
||
<figure id="tbl-6-48">
|
||
<table>
|
||
<tr>
|
||
<th>Input Value</th>
|
||
<th>Result Value</th>
|
||
<th>Comments</th></tr>
|
||
<tr>
|
||
<td>NAN</td>
|
||
<td>QNAN(input)</td>
|
||
<td>If (SRC = SNaN) then #I</td></tr>
|
||
<tr>
|
||
<td><sub>0 ≤ X < 2</sub><sup>-126</sup></td>
|
||
<td>INF</td>
|
||
<td>Positive input denormal or zero; #Z</td></tr>
|
||
<tr>
|
||
<td>-2<sup>-126</sup> < X ≤ -0</td>
|
||
<td>-INF</td>
|
||
<td>Negative input denormal or zero; #Z</td></tr>
|
||
<tr>
|
||
<td>X > 2<sup>126</sup></td>
|
||
<td>+0.0f</td>
|
||
<td></td></tr>
|
||
<tr>
|
||
<td>X < -2<sup>126</sup></td>
|
||
<td>-0.0f</td>
|
||
<td></td></tr>
|
||
<tr>
|
||
<td>X = +∞</td>
|
||
<td>+0.0f</td>
|
||
<td></td></tr>
|
||
<tr>
|
||
<td>X = -∞</td>
|
||
<td>-0.0f</td>
|
||
<td></td></tr>
|
||
<tr>
|
||
<td><sub>X = 2</sub>-n</td>
|
||
<td><sub>2</sub><sup>n</sup></td>
|
||
<td>Exact result (unless input/output is a denormal)</td></tr>
|
||
<tr>
|
||
<td>X = -2<sup>-n</sup></td>
|
||
<td>-2<sup>n</sup></td>
|
||
<td>Exact result (unless input/output is a denormal)</td></tr></table>
|
||
<figcaption><a href='vrcp28ps.html#tbl-6-48'>Table 6-48</a>. VRCP28PS Special Cases</figcaption></figure>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);
|
||
</pre>
|
||
<pre>VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);
|
||
</pre>
|
||
<pre>VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>Invalid (if SNaN input), Divide-by-zero.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>See <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|