175 lines
21 KiB
HTML
175 lines
21 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPERM2F128
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— Permute Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPERM2F128
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— Permute Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.256.66.0F3A.W0 06 /r ib VPERM2F128 ymm1, ymm2, ymm3/m256, imm8</td>
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<td>RV MI</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Permute 128-bit floating-point fields in ymm2 and ymm3/mem using controls from imm8 and store result in ymm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RVMI</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register.</p>
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<figure id="fig-5-21">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="57.65609662000003" x="360.29923832000003" y="119.97055204000003">X0, X1, Y0, or Y1</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="19.963882439999992" x="144.84" y="120.57090779999999">DEST</text>
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<figcaption><a href='vperm2f128.html#fig-5-21'>Figure 5-21</a>. VPERM2F128 Operation</figcaption></figure>
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<p>Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.</p>
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<p>VEX.L must be 1, otherwise the instruction will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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||
</a></h2>
|
||
<h3 id="vperm2f128">VPERM2F128<a class="anchor" href="#vperm2f128">
|
||
¶
|
||
</a></h3>
|
||
<pre>CASE IMM8[1:0] of
|
||
0: DEST[127:0] := SRC1[127:0]
|
||
1: DEST[127:0] := SRC1[255:128]
|
||
2: DEST[127:0] := SRC2[127:0]
|
||
3: DEST[127:0] := SRC2[255:128]
|
||
ESAC
|
||
CASE IMM8[5:4] of
|
||
0: DEST[255:128] := SRC1[127:0]
|
||
1: DEST[255:128] := SRC1[255:128]
|
||
2: DEST[255:128] := SRC2[127:0]
|
||
3: DEST[255:128] := SRC2[255:128]
|
||
ESAC
|
||
IF (imm8[3])
|
||
DEST[127:0] := 0
|
||
FI
|
||
IF (imm8[7])
|
||
DEST[MAXVL-1:128] := 0
|
||
FI
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>VPERM2F128: __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
|
||
</pre>
|
||
<pre>VPERM2F128: __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
|
||
</pre>
|
||
<pre>VPERM2F128: __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>See <span class="not-imported">Table 2-23</span>, “Type 6 Class Exception Conditions.”</p>
|
||
<p>Additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="2">#UD</td>
|
||
<td>If VEX.L = 0</td></tr>
|
||
<tr>
|
||
<td>If VEX.W = 1.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|