98 lines
5.8 KiB
HTML
98 lines
5.8 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VGETMANTSS
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— Extract Float32 Vector of Normalized Mantissa From Float32 Scalar</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VGETMANTSS
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— Extract Float32 Vector of Normalized Mantissa From Float32 Scalar</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.66.0F3A.W0 27 /r ib VGETMANTSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Extract the normalized mantissa from the low float32 element of xmm3/m32 using imm8 for sign control and mantissa interval normalization, store the mantissa to xmm1 under the writemask k1 and merge with the other elements of xmm2.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Convert the single-precision floating values in the low doubleword element of the second source operand (the third operand) to single-precision floating-point value with the mantissa normalization and sign control specified by the imm8 byte, see <a href='vgetmantpd.html#fig-5-15'>Figure 5-15</a>. The converted result is written to the low doubleword element of the destination operand (the first operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.</p>
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<p>The conversion operation is:</p>
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<p>GetMant(x) = ±2<sup>k</sup>|x.significand|</p>
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<p>where:</p>
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<p>1 <= |x.significand| < 2</p>
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<p>Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign. The encoded value of imm8[1:0] and sign control are shown in <a href='vgetmantpd.html#fig-5-15'>Figure 5-15</a>.</p>
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<p>The converted single-precision floating-point result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv.</p>
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<p>The GetMant() function follows <a href='vgetmantpd.html#tbl-5-18'>Table 5-18</a> when dealing with floating-point special numbers.</p>
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<p>If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination operand is unconditionally updated.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>// getmant_fp32(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPS
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</pre>
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<h4 id="vgetmantss--evex-encoded-version-">VGETMANTSS (EVEX encoded version)<a class="anchor" href="#vgetmantss--evex-encoded-version-">
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¶
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</a></h4>
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<pre>SignCtrl[1:0] := IMM8[3:2];
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Interv[1:0] := IMM8[1:0];
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IF k1[0] OR *no writemask*
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THEN DEST[31:0] :=
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getmant_fp32(src, sign_control, normalization_interval)
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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DEST[31:0] := 0
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FI
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FI;
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
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</pre>
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<pre>VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
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</pre>
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<pre>VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
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</pre>
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<pre>VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);
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</pre>
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<pre>VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
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</pre>
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<pre>VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Denormal, Invalid</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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