669 lines
203 KiB
HTML
669 lines
203 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VDBPSADBW
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— Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VDBPSADBW
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— Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W0 42 /r ib VDBPSADBW xmm1 {k1}{z}, xmm2, xmm3/m128, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compute packed SAD word results of unsigned bytes in dword block from xmm2 with unsigned bytes of dword blocks transformed from xmm3/m128 using the shuffle controls in imm8. Results are written to xmm1 under the writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W0 42 /r ib VDBPSADBW ymm1 {k1}{z}, ymm2, ymm3/m256, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compute packed SAD word results of unsigned bytes in dword block from ymm2 with unsigned bytes of dword blocks transformed from ymm3/m256 using the shuffle controls in imm8. Results are written to ymm1 under the writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 42 /r ib VDBPSADBW zmm1 {k1}{z}, zmm2, zmm3/m512, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Compute packed SAD word results of unsigned bytes in dword block from zmm2 with unsigned bytes of dword blocks transformed from zmm3/m512 using the shuffle controls in imm8. Results are written to zmm1 under the writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results in each 64-bit superblock of the destination register.</p>
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<p>Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as follows:</p>
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<ul>
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<li>The lower two word results are calculated each from the SAD operation between a sliding dword element within a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword superblock of the first source operand. The intermediate vector, see “Tmp1” in <a href='vdbpsadbw.html#fig-5-8'>Figure 5-8</a>, is constructed from the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from the first source operand is located at byte offset 0.</li>
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<li>The next two word results are calculated each from the SAD operation between a sliding dword element within a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corresponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in the qword superblock from the first source operand is located at byte offset 4.</li>
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<li>The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the intermediate vector and the second source operand, similarly to PSHUFD.</li></ul>
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<p>The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at 16-bit word granularity.</p>
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<path d="M 204.66 172.37997999999993 L 204.66 171.8999799999999 L 193.92 171.7799799999999 L 193.8 171.7799799999999 L 193.07999999999998 172.25997999999993 L 193.92 172.25997999999993" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 204.18 169.43997999999988 L 203.94 169.49997999999982 L 203.82 169.01997999999992 L 204.06 168.95997999999986" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 336.06 133.49997999999994 L 335.94 133.01997999999992 L 204.06 168.95997999999997 L 204.18 169.43998" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 266.88 256.0799799999999 L 266.52 255.8399799999999 L 260.82 264.8399799999999 L 261.18 265.0799799999999" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 269.22 257.99997999999994 L 268.86 257.6399799999999 L 260.82000000000005 264.7799799999999 L 260.76000000000005 264.8999799999999 L 260.52000000000004 265.73997999999995 L 261.18 265.1399799999999" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 260.76 264.8999799999999 L 261.24 265.0199799999999 L 264.3 254.63997999999992 L 263.82 254.51997999999992" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 344.28000000000003 133.85997999999995 L 344.40000000000003 133.67998 L 343.98 133.43998 L 343.86 133.61997999999994" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 266.94 256.0799799999999 L 266.82 256.2599799999999 L 266.4 256.0199799999999 L 266.52 255.8399799999999" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<path d="M 344.28000000000003 133.85997999999995 L 343.86 133.61997999999994 L 266.52000000000004 255.83997999999997 L 266.94000000000005 256.07998" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="30.36599999999993" x="166.20000000000002" y="21.875980000000027">127+128*n</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.825999999999823" x="251.22" y="21.875980000000027">95+128*n</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.885999999999797" x="323.76" y="21.875980000000027">63+128*n</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.82480000000004" x="397.74" y="21.875980000000027">31+128*n</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="16.387200000000007" x="459.24" y="21.875980000000027">128*n</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="52.67699999999999" x="97.91999999999999" y="31.65598">128-bit Lane of Src2</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="12.088799999999992" x="349.56000000000006" y="33.39607999999987">DW1</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="12.02879999999999" x="418.44000000000005" y="32.37607999999989">DW0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="12.088799999999992" x="205.02000000000004" y="33.21607999999992">DW3</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="12.02879999999999" x="279.00000000000006" y="33.516079999999874">DW2</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="25.285799999999938" x="425.46000000000004" y="50.97607999999991">00B: DW0</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="25.285799999999938" x="425.46000000000004" y="58.95607999999993">01B: DW1</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="25.285799999999938" x="425.46000000000004" y="66.93607999999995">10B: DW2</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="52.75499999999994" x="230.64" y="68.37598000000003">imm8 shuffle control</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="25.285799999999938" x="425.46000000000004" y="74.97607999999991">11B: DW3</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="69.50999999999999" x="305.94" y="80.61598000000004">75310</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="30.36599999999993" x="165.0" y="106.29597999999999">127+128*n</text>
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||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.82599999999985" x="250.01999999999998" y="106.29597999999999">95+128*n</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.88600000000008" x="322.5" y="106.29597999999999">63+128*n</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="26.885999999999797" x="396.54" y="106.29597999999999">31+128*n</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="16.450800000000015" x="458.04" y="106.29597999999999">128*n</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="55.89239999999995" x="101.03999999999996" y="117.27598">128-bit Lane of Tmp1</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="61.13579999999985" x="352.98" y="130.11598000000004">Tmp1 qword superblock</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="69.50999999999999" x="345.0" y="167.19597999999985">39 31 23 15 8</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="72.98999999999997" x="127.97999999999998" y="167.55597999999986">55 47 39 31 24</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="49.81079999999986" x="419.70000000000005" y="176.73597999999993">Tmp1 sliding dword</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="49.7988" x="203.64" y="177.81597999999997">Tmp1 sliding dword</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="69.50999999999999" x="344.4" y="190.59597999999983">31 23 15 7 0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="72.98999999999997" x="126.83999999999999" y="191.7359799999998">63 55 47 39 32</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="61.69139999999982" x="422.1" y="199.9559799999999">Src1 stationary dword 0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="61.69139999999999" x="203.88" y="203.1959799999999">Src1 stationary dword 1</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999987pt; fill: #000" textLength="59.273999999999944" x="350.1" y="211.58397999999994">_ _ _ _</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999987pt; fill: #000" textLength="59.274" x="132.78" y="212.18397999999996">_ _ _ _</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.430256259500084pt; fill: #000" textLength="64.85992844046046" x="347.1" y="223.0932404565458">abs abs abs abs</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.430256259500084pt; fill: #000" textLength="64.7995727604605" x="129.72" y="223.75324045654583">abs abs abs abs</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999997pt; fill: #000" textLength="5.175000000000011" x="373.74" y="261.80397999999997">+</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999997pt; fill: #000" textLength="5.175000000000011" x="156.60000000000002" y="262.04398">+</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="69.50999999999999" x="394.62" y="266.7359799999999">31 23 15 7 0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="49.79939999999982" x="290.52" y="272.4359799999999">Tmp1 sliding dword</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="49.79759999999993" x="470.58" y="276.6959799999999">Tmp1 sliding dword</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="42.56999999999999" x="214.5" y="286.1759799999998">63 55 47</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="69.50999999999999" x="394.44" y="290.13597999999985">31 23 15 7 0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="61.65899999999999" x="290.7" y="296.0759799999999">Src1 stationary dword 1</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="61.68240000000009" x="472.08" y="299.91597999999993">Src1 stationary dword 0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999987pt; fill: #000" textLength="59.27399999999997" x="220.02" y="306.44397999999995">____</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999987pt; fill: #000" textLength="59.274" x="400.14" y="311.06397999999996">____</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.430256259500084pt; fill: #000" textLength="64.7995727604605" x="217.02" y="317.9532404565458">abs abs abs abs</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.430256259500084pt; fill: #000" textLength="64.79957276046053" x="397.08" y="322.5732404565458">abs abs abs abs</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 11.276999999999997pt; fill: #000" textLength="5.175000000000011" x="424.02" y="360.80397999999997">+</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="6.989999999999981" x="168.3" y="366.21597999999994">63</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="7.049999999999983" x="241.08" y="366.21597999999994">47</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="7.050000000000011" x="313.62" y="366.21597999999994">31</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="6.990000000000009" x="387.6" y="366.21597999999994">15</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518pt; fill: #000" textLength="3.509999999999991" x="449.1" y="366.21597999999994">0</text>
|
||
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.517999999999972pt; fill: #000" textLength="75.53279999999994" x="79.02" y="377.1359799999999">Destination qword superblock</text></g></svg>
|
||
<figcaption><a href='vdbpsadbw.html#fig-5-8'>Figure 5-8</a>. 64-bit Super Block of SAD Operation in VDBPSADBW</figcaption></figure>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="vdbpsadbw--evex-encoded-versions-">VDBPSADBW (EVEX Encoded Versions)<a class="anchor" href="#vdbpsadbw--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
|
||
Selection of quadruplets:
|
||
FOR I = 0 to VL step 128
|
||
TMP1[I+31:I] := select (SRC2[I+127: I], imm8[1:0])
|
||
TMP1[I+63: I+32] := select (SRC2[I+127: I], imm8[3:2])
|
||
TMP1[I+95: I+64] := select (SRC2[I+127: I], imm8[5:4])
|
||
TMP1[I+127: I+96] := select (SRC2[I+127: I], imm8[7:6])
|
||
END FOR
|
||
SAD of quadruplets:
|
||
FOR I =0 to VL step 64
|
||
TMP_DEST[I+15:I] := ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
|
||
ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +
|
||
ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +
|
||
ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])
|
||
TMP_DEST[I+31: I+16] := ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +
|
||
ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +
|
||
ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +
|
||
ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])
|
||
TMP_DEST[I+47: I+32] := ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +
|
||
ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +
|
||
ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +
|
||
ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])
|
||
TMP_DEST[I+63: I+48] := ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +
|
||
ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +
|
||
ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +
|
||
ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])
|
||
ENDFOR
|
||
FORj:= 0TOKL-1
|
||
i:= j*16
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+15:i] := TMP_DEST[i+15:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
THEN *DEST[i+15:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+15:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VDBPSADBW __m512i _mm512_dbsad_epu8(__m512i a, __m512i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__mmask32 m, __m512i a, __m512i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m256i _mm256_dbsad_epu8(__m256i a, __m256i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__mmask16 m, __m256i a, __m256i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m128i _mm_mask_dbsad_epu8(__m128i s, __mmask8 m, __m128i a, __m128i b int imm8);
|
||
</pre>
|
||
<pre>VDBPSADBW __m128i _mm_maskz_dbsad_epu8(__mmask8 m, __m128i a, __m128i b int imm8);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>See Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|