125 lines
5.3 KiB
HTML
125 lines
5.3 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTNEPS2BF16
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— Convert Packed Single Data to Packed BF16 Data</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTNEPS2BF16
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— Convert Packed Single Data to Packed BF16 Data</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1{k1}{z}, xmm2/m128/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512_BF16</td>
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<td>Convert packed single data from xmm2/m128 to packed BF16 data in xmm1 with writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1{k1}{z}, ymm2/m256/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512_BF16</td>
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<td>Convert packed single data from ymm2/m256 to packed BF16 data in xmm1 with writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W0 72 /r VCVTNEPS2BF16 ymm1{k1}{z}, zmm2/m512/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F AVX512_BF16</td>
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<td>Convert packed single data from zmm2/m512 to packed BF16 data in ymm1 with writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Converts one SIMD register of packed single data into a single register of packed BF16 data.</p>
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<p>This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and input denormals are always treated as zero. MXCSR is not consulted nor updated.</p>
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<p>As the instruction operand encoding table shows, the EVEX.vvvv field is not used for encoding an operand. EVEX.vvvv is reserved and must be 0b1111 otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>Define convert_fp32_to_bfloat16(x):
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IF x is zero or denormal:
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dest[15] := x[31] // sign preserving zero (denormal go to zero)
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dest[14:0] := 0
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ELSE IF x is infinity:
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dest[15:0] := x[31:16]
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ELSE IF x is NAN:
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dest[15:0] := x[31:16] // truncate and set MSB of the mantissa to force QNAN
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dest[6] := 1
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ELSE // normal number
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LSB := x[16]
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rounding_bias := 0x00007FFF + LSB
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temp[31:0] := x[31:0] + rounding_bias // integer add
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dest[15:0] := temp[31:16]
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RETURN dest
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</pre>
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<h4 id="vcvtneps2bf16-dest--src">VCVTNEPS2BF16 dest, src<a class="anchor" href="#vcvtneps2bf16-dest--src">
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¶
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</a></h4>
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<pre>VL = (128, 256, 512)
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KL = VL/16
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origdest := dest
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FOR i := 0 to KL/2-1:
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IF k1[ i ] or *no writemask*:
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IF src is memory and evex.b == 1:
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t := src.fp32[0]
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ELSE:
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t := src.fp32[ i ]
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dest.word[i] := convert_fp32_to_bfloat16(t)
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ELSE IF *zeroing*:
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dest.word[ i ] := 0
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ELSE: // Merge masking, dest element unchanged
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dest.word[ i ] := origdest.word[ i ]
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DEST[MAXVL-1:VL/2] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128);
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</pre>
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<pre>VCVTNEPS2BF16 __m128bh _mm_mask_cvtneps_pbh (__m128bh, __mmask8, __m128);
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</pre>
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<pre>VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8, __m128);
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</pre>
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<pre>VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256);
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</pre>
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<pre>VCVTNEPS2BF16 __m128bh _mm256_mask_cvtneps_pbh (__m128bh, __mmask8, __m256);
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</pre>
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<pre>VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8, __m256);
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</pre>
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<pre>VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512);
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</pre>
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<pre>VCVTNEPS2BF16 __m256bh _mm512_mask_cvtneps_pbh (__m256bh, __mmask16, __m512);
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</pre>
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<pre>VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16, __m512);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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