417 lines
38 KiB
HTML
417 lines
38 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>UNPCKLPS
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— Unpack and Interleave Low Packed Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>UNPCKLPS
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— Unpack and Interleave Low Packed Single Precision Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 14 /r UNPCKLPS xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of xmm1 and xmm2/m128.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 14 /r VUNPCKLPS xmm1,xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of xmm2 and xmm3/m128.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 14 /r VUNPCKLPS ymm1,ymm2,ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of ymm2 and ymm3/m256.</td></tr>
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<tr>
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<td>EVEX.128.0F.W0 14 /r VUNPCKLPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of xmm2 and xmm3/mem and write result to xmm1 subject to write mask k1.</td></tr>
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<tr>
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<td>EVEX.256.0F.W0 14 /r VUNPCKLPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of ymm2 and ymm3/mem and write result to ymm1 subject to write mask k1.</td></tr>
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<tr>
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<td>EVEX.512.0F.W0 14 /r VUNPCKLPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Unpacks and Interleaves single precision floating-point values from low quadwords of zmm2 and zmm3/m512/m32bcst and write result to zmm1 subject to write mask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs an interleaved unpack of the low single precision floating-point values from the first source operand and the second source operand.</p>
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<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.</p>
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<p>VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<path d="M 197.70000000000002 95.27997999999991 L 199.20000000000002 99.29997999999989 L 183.66000000000003 100.61997999999994 L 196.14000000000001 91.25997999999993" style="fill: rgb(0%, 0%, 0%); fill-rule: evenodd"></path>
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<path d="M 253.20000000000002 75.17997999999989 L 252.48000000000002 73.31997999999987 L 197.76000000000002 94.19997999999987 L 198.48000000000002 96.05997999999988" style="fill: rgb(0%, 0%, 0%); fill-rule: nonzero"></path>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="269.1524851" x="172.8" y="43.83087779999994">X7 X6 X5 X4 X3 X2 X1 X0</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.47438109999996pt; fill: #000" textLength="303.8324851" x="138.12" y="70.89084209999987">SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.474416799999972pt; fill: #000" textLength="303.8324851" x="138.12" y="111.39087779999988">DEST Y5 X5 Y4 X4 Y1 X1 Y0 X0</text></g></svg>
|
||
<figcaption><a href='unpcklps.html#fig-4-28'>Figure 4-28</a>. VUNPCKLPS Operation</figcaption></figure>
|
||
<p>EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
|
||
<p>EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.</p>
|
||
<p>EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="vunpcklps--evex-encoded-version-when-src2-is-a-zmm-register-">VUNPCKLPS (EVEX Encoded Version When SRC2 is a ZMM Register)<a class="anchor" href="#vunpcklps--evex-encoded-version-when-src2-is-a-zmm-register-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
IF VL >= 128
|
||
TMP_DEST[31:0] := SRC1[31:0]
|
||
TMP_DEST[63:32] := SRC2[31:0]
|
||
TMP_DEST[95:64] := SRC1[63:32]
|
||
TMP_DEST[127:96] := SRC2[63:32]
|
||
FI;
|
||
IF VL >= 256
|
||
TMP_DEST[159:128] := SRC1[159:128]
|
||
TMP_DEST[191:160] := SRC2[159:128]
|
||
TMP_DEST[223:192] := SRC1[191:160]
|
||
TMP_DEST[255:224] := SRC2[191:160]
|
||
FI;
|
||
IF VL >= 512
|
||
TMP_DEST[287:256] := SRC1[287:256]
|
||
TMP_DEST[319:288] := SRC2[287:256]
|
||
TMP_DEST[351:320] := SRC1[319:288]
|
||
TMP_DEST[383:352] := SRC2[319:288]
|
||
TMP_DEST[415:384] := SRC1[415:384]
|
||
TMP_DEST[447:416] := SRC2[415:384]
|
||
TMP_DEST[479:448] := SRC1[447:416]
|
||
TMP_DEST[511:480] := SRC2[447:416]
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE *zeroing-masking*
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="vunpcklps--evex-encoded-version-when-src2-is-memory-">VUNPCKLPS (EVEX Encoded Version When SRC2 is Memory)<a class="anchor" href="#vunpcklps--evex-encoded-version-when-src2-is-memory-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 31
|
||
IF (EVEX.b = 1)
|
||
THEN TMP_SRC2[i+31:i] := SRC2[31:0]
|
||
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i]
|
||
FI;
|
||
ENDFOR;
|
||
IF VL >= 128
|
||
TMP_DEST[31:0] := SRC1[31:0]
|
||
TMP_DEST[63:32] := TMP_SRC2[31:0]
|
||
TMP_DEST[95:64] := SRC1[63:32]
|
||
TMP_DEST[127:96] := TMP_SRC2[63:32]
|
||
FI;
|
||
IF VL >= 256
|
||
TMP_DEST[159:128] := SRC1[159:128]
|
||
TMP_DEST[191:160] := TMP_SRC2[159:128]
|
||
TMP_DEST[223:192] := SRC1[191:160]
|
||
TMP_DEST[255:224] := TMP_SRC2[191:160]
|
||
FI;
|
||
IF VL >= 512
|
||
TMP_DEST[287:256] := SRC1[287:256]
|
||
TMP_DEST[319:288] := TMP_SRC2[287:256]
|
||
TMP_DEST[351:320] := SRC1[319:288]
|
||
TMP_DEST[383:352] := TMP_SRC2[319:288]
|
||
TMP_DEST[415:384] := SRC1[415:384]
|
||
TMP_DEST[447:416] := TMP_SRC2[415:384]
|
||
TMP_DEST[479:448] := SRC1[447:416]
|
||
TMP_DEST[511:480] := TMP_SRC2[447:416]
|
||
FI;
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
|
||
ELSE
|
||
IF *merging-masking*
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE *zeroing-masking* ; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="unpcklps--vex-256-encoded-version-">UNPCKLPS (VEX.256 Encoded Version)<a class="anchor" href="#unpcklps--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31:0] := SRC1[31:0]
|
||
DEST[63:32] := SRC2[31:0]
|
||
DEST[95:64] := SRC1[63:32]
|
||
DEST[127:96] := SRC2[63:32]
|
||
DEST[159:128] := SRC1[159:128]
|
||
DEST[191:160] := SRC2[159:128]
|
||
DEST[223:192] := SRC1[191:160]
|
||
DEST[255:224] := SRC2[191:160]
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vunpcklps--vex-128-encoded-version-">VUNPCKLPS (VEX.128 Encoded Version)<a class="anchor" href="#vunpcklps--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31:0] := SRC1[31:0]
|
||
DEST[63:32] := SRC2[31:0]
|
||
DEST[95:64] := SRC1[63:32]
|
||
DEST[127:96] := SRC2[63:32]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="unpcklps--128-bit-legacy-sse-version-">UNPCKLPS (128-bit Legacy SSE Version)<a class="anchor" href="#unpcklps--128-bit-legacy-sse-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31:0] := SRC1[31:0]
|
||
DEST[63:32] := SRC2[31:0]
|
||
DEST[95:64] := SRC1[63:32]
|
||
DEST[127:96] := SRC2[63:32]
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);
|
||
</pre>
|
||
<pre>UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
|
||
</pre>
|
||
<pre>VUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instructions, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|