119 lines
5.7 KiB
HTML
119 lines
5.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD
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— Dot Product of Signed/Unsigned Bytes with DwordAccumulation</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD
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— Dot Product of Signed/Unsigned Bytes with DwordAccumulation</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.F2.0F38.W0 5E 11:rrr:bbb TDPBSSD tmm1, tmm2, tmm3</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-INT8</td>
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<td>Matrix multiply signed byte elements from tmm2 by signed byte elements from tmm3 and accumulate the dword elements in tmm1.</td></tr>
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<tr>
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<td>VEX.128.F3.0F38.W0 5E 11:rrr:bbb TDPBSUD tmm1, tmm2, tmm3</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-INT8</td>
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<td>Matrix multiply signed byte elements from tmm2 by unsigned byte elements from tmm3 and accumulate the dword elements in tmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 5E 11:rrr:bbb TDPBUSD tmm1, tmm2, tmm3</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-INT8</td>
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<td>Matrix multiply unsigned byte elements from tmm2 by signed byte elements from tmm3 and accumulate the dword elements in tmm1.</td></tr>
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<tr>
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<td>VEX.128.NP.0F38.W0 5E 11:rrr:bbb TDPBUUD tmm1, tmm2, tmm3</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-INT8</td>
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<td>Matrix multiply unsigned byte elements from tmm2 by unsigned byte elements from tmm3 and accumulate the dword elements in tmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>VEX.vvvv (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>For each possible combination of (row of tmm2, column of tmm3), the instruction performs a set of SIMD dot-products on all corresponding four byte elements, one from tmm2 and one from tmm3, adds the results of those dot-products, and then accumulates the result into the corresponding row and column of tmm1. Each dword in input tiles tmm2 and tmm3 is interpreted as four byte elements. These may be signed or unsigned. Each letter in the two-letter pattern SU, US, SS, UU indicates the signed/unsigned nature of the values in tmm2 and tmm3, respectively.</p>
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<p>Any attempt to execute the TDPBSSD/TDPBSUD/TDPBUSD/TDPBUUD instructions inside an Intel TSX transaction will result in a transaction abort.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>define DPBD(c,x,y):// arguments are dwords
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if *x operand is signed*:
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extend_src1 := SIGN_EXTEND
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else:
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extend_src1 := ZERO_EXTEND
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if *y operand is signed*:
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extend_src2 := SIGN_EXTEND
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else:
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extend_src2 := ZERO_EXTEND
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p0dword := extend_src1(x.byte[0]) * extend_src2(y.byte[0])
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p1dword := extend_src1(x.byte[1]) * extend_src2(y.byte[1])
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p2dword := extend_src1(x.byte[2]) * extend_src2(y.byte[2])
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p3dword := extend_src1(x.byte[3]) * extend_src2(y.byte[3])
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c := c + p0dword + p1dword + p2dword + p3dword
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</pre>
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<h3 id="tdpbssd--tdpbsud--tdpbusd--tdpbuud-tsrcdest--tsrc1--tsrc2--register-only-version-">TDPBSSD, TDPBSUD, TDPBUSD, TDPBUUD tsrcdest, tsrc1, tsrc2 (Register Only Version)<a class="anchor" href="#tdpbssd--tdpbsud--tdpbusd--tdpbuud-tsrcdest--tsrc1--tsrc2--register-only-version-">
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¶
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</a></h3>
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<pre>// C = m x n (tsrcdest), A = m x k (tsrc1), B = k x n (tsrc2)
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tsrc1_elements_per_row := tsrc1.colsb / 4
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tsrc2_elements_per_row := tsrc2.colsb / 4
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tsrcdest_elements_per_row := tsrcdest.colsb / 4
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for m in 0 ... tsrcdest.rows-1:
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tmp := tsrcdest.row[m]
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for k in 0 ... tsrc1_elements_per_row-1:
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for n in 0 ... tsrcdest_elements_per_row-1:
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DPBD( tmp.dword[n], tsrc1.row[m].dword[k], tsrc2.row[k].dword[n] )
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write_row_and_zero(tsrcdest, m, tmp, tsrcdest.colsb)
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zero_upper_rows(tsrcdest, tsrcdest.rows)
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zero_tilecfg_start()
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>TDPBSSD void _tile_dpbssd(__tile dst, __tile src1, __tile src2);
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</pre>
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<pre>TDPBSUD void _tile_dpbsud(__tile dst, __tile src1, __tile src2);
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</pre>
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<pre>TDPBUSD void _tile_dpbusd(__tile dst, __tile src1, __tile src2);
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</pre>
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<pre>TDPBUUD void _tile_dpbuud(__tile dst, __tile src1, __tile src2);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
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¶
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</a></h2>
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<p>AMX-E4; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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