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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVSD
— Move or Merge Scalar Double Precision Floating-Point Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVSD
— Move or Merge Scalar Double Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F 10 /r MOVSD xmm1, xmm2</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double precision floating-point value from xmm2 to xmm1 register.</td></tr>
<tr>
<td>F2 0F 10 /r MOVSD xmm1, m64</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Load scalar double precision floating-point value from m64 to xmm1 register.</td></tr>
<tr>
<td>F2 0F 11 /r MOVSD xmm1/m64, xmm2</td>
<td>C</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double precision floating-point value from xmm2 register to xmm1/m64.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.WIG 10 /r VMOVSD xmm1, xmm2, xmm3</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double precision floating-point value from xmm2 and xmm3 to xmm1 register.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.WIG 10 /r VMOVSD xmm1, m64</td>
<td>D</td>
<td>V/V</td>
<td>AVX</td>
<td>Load scalar double precision floating-point value from m64 to xmm1 register.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.WIG 11 /r VMOVSD xmm1, xmm2, xmm3</td>
<td>E</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.WIG 11 /r VMOVSD m64, xmm1</td>
<td>C</td>
<td>V/V</td>
<td>AVX</td>
<td>Store scalar double precision floating-point value from xmm1 register to m64.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W1 10 /r VMOVSD xmm1 {k1}{z}, xmm2, xmm3</td>
<td>B</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W1 10 /r VMOVSD xmm1 {k1}{z}, m64</td>
<td>F</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Load scalar double precision floating-point value from m64 to xmm1 register under writemask k1.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W1 11 /r VMOVSD xmm1 {k1}{z}, xmm2, xmm3</td>
<td>E</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge scalar double precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W1 11 /r VMOVSD m64 {k1}, xmm1</td>
<td>G</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Store scalar double precision floating-point value from xmm1 register to m64 under writemask k1.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>C</td>
<td>N/A</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>D</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>E</td>
<td>N/A</td>
<td>ModRM:r/m (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td></tr>
<tr>
<td>F</td>
<td>Tuple1 Scalar</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>G</td>
<td>Tuple1 Scalar</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Moves a scalar double precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. This instruction can be used to move a double precision floating-point value to and from the low quadword of an XMM register and a 64-bit memory location, or to move a double precision floating-point value between the low quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.</p>
<p>Legacy version: When the source and destination operands are XMM registers, bits MAXVL:64 of the destination operand remains unchanged. When the source operand is a memory location and destination operand is an XMM</p>
<p>registers, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAXVL:128 of the destination operand remains unchanged.</p>
<p>VEX and EVEX encoded register-register syntax: Moves a scalar double precision floating-point value from the second source operand (the third operand) to the low quadword element of the destination operand (the first operand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
<p>VEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAXVL:64 of the destination operand is cleared to all 0s.</p>
<p>EVEX encoded versions: The low quadword of the destination is updated according to the writemask.</p>
<p>Note: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instruction will #UD.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="vmovsd--evex-llig-f2-0f-10--r--vmovsd-xmm1--m64-with-support-for-32-registers-">VMOVSD (EVEX.LLIG.F2.0F 10 /r: VMOVSD xmm1, m64 With Support for 32 Registers)<a class="anchor" href="#vmovsd--evex-llig-f2-0f-10--r--vmovsd-xmm1--m64-with-support-for-32-registers-">
</a></h3>
<pre>IF k1[0] or *no writemask*
THEN DEST[63:0] := SRC[63:0]
ELSE
IF *merging-masking* ; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE ; zeroing-masking
THEN DEST[63:0] := 0
FI;
FI;
DEST[MAXVL-1:64] := 0
</pre>
<h3 id="vmovsd--evex-llig-f2-0f-11--r--vmovsd-m64--xmm1-with-support-for-32-registers-">VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD m64, xmm1 With Support for 32 Registers)<a class="anchor" href="#vmovsd--evex-llig-f2-0f-11--r--vmovsd-m64--xmm1-with-support-for-32-registers-">
</a></h3>
<pre>IF k1[0] or *no writemask*
THEN DEST[63:0] := SRC[63:0]
ELSE *DEST[63:0] remains unchanged* ; merging-masking
FI;
</pre>
<h3 id="vmovsd--evex-llig-f2-0f-11--r--vmovsd-xmm1--xmm2--xmm3-">VMOVSD (EVEX.LLIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)<a class="anchor" href="#vmovsd--evex-llig-f2-0f-11--r--vmovsd-xmm1--xmm2--xmm3-">
</a></h3>
<pre>IF k1[0] or *no writemask*
THEN DEST[63:0] := SRC2[63:0]
ELSE
IF *merging-masking* ; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE ; zeroing-masking
THEN DEST[63:0] := 0
FI;
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="movsd--128-bit-legacy-sse-version--movsd-xmm1--xmm2-">MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, xmm2)<a class="anchor" href="#movsd--128-bit-legacy-sse-version--movsd-xmm1--xmm2-">
</a></h3>
<pre>DEST[63:0] := SRC[63:0]
DEST[MAXVL-1:64] (Unmodified)
</pre>
<h3 id="vmovsd--vex-128-f2-0f-11--r--vmovsd-xmm1--xmm2--xmm3-">VMOVSD (VEX.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)<a class="anchor" href="#vmovsd--vex-128-f2-0f-11--r--vmovsd-xmm1--xmm2--xmm3-">
</a></h3>
<pre>DEST[63:0] := SRC2[63:0]
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vmovsd--vex-128-f2-0f-10--r--vmovsd-xmm1--xmm2--xmm3-">VMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)<a class="anchor" href="#vmovsd--vex-128-f2-0f-10--r--vmovsd-xmm1--xmm2--xmm3-">
</a></h3>
<pre>DEST[63:0] := SRC2[63:0]
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vmovsd--vex-128-f2-0f-10--r--vmovsd-xmm1--m64-">VMOVSD (VEX.128.F2.0F 10 /r: VMOVSD xmm1, m64)<a class="anchor" href="#vmovsd--vex-128-f2-0f-10--r--vmovsd-xmm1--m64-">
</a></h3>
<pre>DEST[63:0] := SRC[63:0]
DEST[MAXVL-1:64] := 0
</pre>
<h3 id="movsd-vmovsd--128-bit-versions--movsd-m64--xmm1-or-vmovsd-m64--xmm1-">MOVSD/VMOVSD (128-bit Versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)<a class="anchor" href="#movsd-vmovsd--128-bit-versions--movsd-m64--xmm1-or-vmovsd-m64--xmm1-">
</a></h3>
<pre>DEST[63:0] := SRC[63:0]
</pre>
<h3 id="movsd--128-bit-legacy-sse-version--movsd-xmm1--m64-">MOVSD (128-bit Legacy SSE Version: MOVSD xmm1, m64)<a class="anchor" href="#movsd--128-bit-legacy-sse-version--movsd-xmm1--m64-">
</a></h3>
<pre>DEST[63:0] := SRC[63:0]
DEST[127:64] := 0
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>VMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);
</pre>
<pre>VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);
</pre>
<pre>VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);
</pre>
<pre>VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);
</pre>
<pre>VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);
</pre>
<pre>MOVSD __m128d _mm_load_sd (double *p)
</pre>
<pre>MOVSD void _mm_store_sd (double *p, __m128d a)
</pre>
<pre>MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)
</pre>
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions,” additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If VEX.vvvv != 1111B.</td></tr></table>
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-58</span>, “Type E10 Class Exception Conditions.”</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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