124 lines
6.2 KiB
HTML
124 lines
6.2 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVNTPD
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— Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVNTPD
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— Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 2B /r MOVNTPD m128, xmm1</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move packed double precision values in xmm1 to m128 using non-temporal hint.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG 2B /r VMOVNTPD m128, xmm1</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move packed double precision values in xmm1 to m128 using non-temporal hint.</td></tr>
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<tr>
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<td>VEX.256.66.0F.WIG 2B /r VMOVNTPD m256, ymm1</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move packed double precision values in ymm1 to m256 using non-temporal hint.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 2B /r VMOVNTPD m128, xmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move packed double precision values in xmm1 to m128 using non-temporal hint.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W1 2B /r VMOVNTPD m256, ymm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Move packed double precision values in ymm1 to m256 using non-temporal hint.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W1 2B /r VMOVNTPD m512, zmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move packed double precision values in zmm1 to m512 using non-temporal hint.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<sup>1</sup><a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<blockquote>
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<p>1. ModRM.MOD != 011B</p></blockquote>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Full Mem</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Moves the packed double precision floating-point values in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double precision, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.</p>
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<p>The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see “Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the IA-32 Intel Architecture Software Developer’s Manual, Volume 1.</p>
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<p>Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors might use different memory types to read/write the destination memory locations.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vmovntpd--evex-encoded-versions-">VMOVNTPD (EVEX Encoded Versions)<a class="anchor" href="#vmovntpd--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>VL = 128, 256, 512
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DEST[VL-1:0] := SRC[VL-1:0]
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="movntpd--legacy-and-vex-versions-">MOVNTPD (Legacy and VEX Versions)<a class="anchor" href="#movntpd--legacy-and-vex-versions-">
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¶
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</a></h3>
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<pre>DEST := SRC
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VMOVNTPD void _mm512_stream_pd(double * p, __m512d a);
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</pre>
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<pre>VMOVNTPD void _mm256_stream_pd (double * p, __m256d a);
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</pre>
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<pre>MOVNTPD void _mm_stream_pd (double * p, __m128d a);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see Exceptions Type1.SSE2 in <span class="not-imported">Table 2-18</span>, “Type 1 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-45</span>, “Type E1NF Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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