183 lines
10 KiB
HTML
183 lines
10 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>INVEPT
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— Invalidate Translations Derived from EPT</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>INVEPT
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— Invalidate Translations Derived from EPT</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 80 INVEPT r64, m128</td>
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<td>RM</td>
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<td>Invalidates EPT-derived entries in the TLBs and paging-structure caches (in 64-bit mode).</td></tr>
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<tr>
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<td>66 0F 38 80 INVEPT r32, m128</td>
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<td>RM</td>
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<td>Invalidates EPT-derived entries in the TLBs and paging-structure caches (outside 64-bit mode).</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td>Operand 1</td>
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<td>Operand 2</td>
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<td>Operand 3</td>
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<td>Operand 4</td></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>NA</td>
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<td>NA</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches that were derived from extended page tables (EPT). (See Chapter 29, “VMX Support for Address Translation.”) Invalidation is based on the <strong>INVEPT type</strong> specified in the register operand and the <strong>INVEPT descriptor</strong> specified in the memory operand.</p>
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<p>Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D; in 64-bit mode, the register operand has 64 bits (the instruction cannot be executed in compatibility mode).</p>
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<p>The INVEPT types supported by a logical processors are reported in the IA32_VMX_EPT_VPID_CAP MSR (see Appendix A, “VMX Capability Reporting Facility”). There are two INVEPT types currently defined:</p>
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<ul>
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<li>Single-context invalidation. If the INVEPT type is 1, the logical processor invalidates all mappings associated with bits 51:12 of the EPT pointer (EPTP) specified in the INVEPT descriptor. It may invalidate other mappings as well.</li>
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<li>Global invalidation: If the INVEPT type is 2, the logical processor invalidates mappings associated with all EPTPs.</li></ul>
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<p>If an unsupported INVEPT type is specified, the instruction fails.</p>
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<p>INVEPT invalidates all the specified mappings for the indicated EPTP(s) regardless of the VPID and PCID values with which those mappings may be associated.</p>
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<p>The INVEPT descriptor comprises 128 bits and contains a 64-bit EPTP value in bits 63:0 (see <a href='invept.html#fig-31-1'>Figure 31-1</a>).</p>
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<figure id="fig-31-1">
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<svg style="width: 455.616pt; height: 91.08001199999997pt" viewBox="109.64 0.0 384.68 80.90000999999998">
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<g xmlns="http://www.w3.org/2000/svg" style="stroke: none; fill: none">
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<rect height="74.94" style="fill: rgb(0%, 0%, 0%)" width="0.48" x="112.14" y="0.48000999999999294"></rect>
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<rect height="74.94" style="fill: rgb(0%, 0%, 0%)" width="0.47998" x="491.34000000000003" y="0.48000999999999294"></rect>
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<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="379.68" x="112.14" y="0.0"></rect>
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<rect height="0.48" style="fill: rgb(0%, 0%, 0%)" width="379.68" x="112.14" y="75.42000999999999"></rect>
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<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="306.6" x="153.60000000000002" y="28.800009999999986"></rect>
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<rect height="18.54" style="fill: rgb(0%, 0%, 0%)" width="1.02" x="459.18" y="29.280009999999947"></rect>
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<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="306.54" x="153.12" y="46.80000999999996"></rect>
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<rect height="18.48" style="fill: rgb(0%, 0%, 0%)" width="1.02" x="153.12" y="28.800009999999986"></rect>
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<rect height="18.0" style="fill: rgb(70%, 70%, 70%)" width="153.06" x="153.60000000000002" y="29.280009999999947"></rect>
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<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="153.60000000000002" x="153.60000000000002" y="28.800009999999986"></rect>
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<rect height="18.54" style="fill: rgb(0%, 0%, 0%)" width="1.02" x="306.18" y="29.280009999999947"></rect>
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<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="153.54" x="153.12" y="46.80000999999996"></rect>
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<rect height="18.48" style="fill: rgb(0%, 0%, 0%)" width="1.02" x="153.12" y="28.800009999999986"></rect>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 10.107835200000011pt; fill: #000" textLength="14.993288879999994" x="150.0" y="27.591079199999967">127</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 10.107835200000011pt; fill: #000" textLength="21.53168155999998" x="295.5" y="27.591079199999967">6463</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 10.1078352pt; fill: #000" textLength="5.035803199999975" x="456.05517296" y="27.591079199999957">0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 10.107835200000011pt; fill: #000" textLength="98.91911552000005" x="182.40002643999998" y="42.89140715999997">Reserved (must be zero)</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 10.107835200000011pt; fill: #000" textLength="79.2351027599999" x="344.48314904" y="42.89140715999997">EPT pointer (EPTP)</text></g></svg>
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<figcaption><a href='invept.html#fig-31-1'>Figure 31-1</a>. INVEPT Descriptor</figcaption></figure>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
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THEN #UD;
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ELSIF in VMX non-root operation
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THEN VM exit;
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ELSIF CPL > 0
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THEN #GP(0);
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ELSE
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INVEPT_TYPE := value of register operand;
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IF IA32_VMX_EPT_VPID_CAP MSR indicates that processor does not support INVEPT_TYPE
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THEN VMfail(Invalid operand to INVEPT/INVVPID);
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ELSE // INVEPT_TYPE must be 1 or 2
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INVEPT_DESC := value of memory operand;
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EPTP := INVEPT_DESC[63:0];
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CASE INVEPT_TYPE OF
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1:
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// single-context invalidation
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IF VM entry with the “enable EPT“ VM execution control set to 1
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would fail due to the EPTP value
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THEN VMfail(Invalid operand to INVEPT/INVVPID);
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ELSE
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Invalidate mappings associated with EPTP[51:12];
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VMsucceed;
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FI;
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BREAK;
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2:
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// global invalidation
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Invalidate mappings associated with all EPTPs;
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VMsucceed;
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BREAK;
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ESAC;
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FI;
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>See the operation section and Section 31.2.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If the current privilege level is not 0.</td></tr>
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<tr>
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<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register contains an unusable segment.</td></tr>
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<tr>
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<td>If the source operand is located in an execute-only code segment.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs in accessing the memory operand.</td></tr>
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<tr>
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<td rowspan="2">#SS(0)</td>
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<td>If the memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>If the SS register contains an unusable segment.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If not in VMX operation.</td></tr>
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<tr>
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<td>If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).</td></tr>
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<tr>
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<td>If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The INVEPT instruction is not recognized in real-address mode.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The INVEPT instruction is not recognized in virtual-8086 mode.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The INVEPT instruction is not recognized in compatibility mode.</td></tr></table>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If the current privilege level is not 0.</td></tr>
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<tr>
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<td>If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs in accessing the memory operand.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If the memory operand is in the SS segment and the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If not in VMX operation.</td></tr>
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<tr>
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<td>If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).</td></tr>
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<tr>
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<td>If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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