145 lines
6.2 KiB
HTML
145 lines
6.2 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>AESENCLAST
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— Perform Last Round of an AES Encryption Flow</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>AESENCLAST
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— Perform Last Round of an AES Encryption Flow</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 DD /r AESENCLAST xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AES</td>
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<td>Perform the last round of an AES encryption flow, using one 128-bit data (state) from xmm1 with one 128-bit round key from xmm2/m128.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG DD /r VAESENCLAST xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AES AVX</td>
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<td>Perform the last round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from xmm3/m128; store the result in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG DD /r VAESENCLAST ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>VAES</td>
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<td>Perform the last round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from ymm3/m256; store the result in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.WIG DD /r VAESENCLAST xmm1, xmm2, xmm3/m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>VAES AVX512VL</td>
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<td>Perform the last round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from xmm3/m128; store the result in xmm1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.WIG DD /r VAESENCLAST ymm1, ymm2, ymm3/m256</td>
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<td>C</td>
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<td>V/V</td>
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<td>VAES AVX512VL</td>
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<td>Perform the last round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from ymm3/m256; store the result in ymm1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.WIG DD /r VAESENCLAST zmm1, zmm2, zmm3/m512</td>
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<td>C</td>
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<td>V/V</td>
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<td>VAES AVX512F</td>
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<td>Perform the last round of an AES encryption flow, using four 128-bit data (state) from zmm2 with four 128-bit round keys from zmm3/m512; store the result in zmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>This instruction performs the last round of an AES encryption flow using one/two/four (depending on vector length) 128-bit data (state) from the first source operand with one/two/four (depending on vector length) round key(s) from the second source operand, and stores the result in the destination operand.</p>
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<p>VEX and EVEX encoded versions of the instruction allows 3-operand (non-destructive) operation. The legacy encoded versions of the instruction require that the first source operand and the destination operand are the same and must be an XMM register.</p>
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<p>The EVEX encoded form of this instruction does not support memory fault suppression.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="aesenclast">AESENCLAST<a class="anchor" href="#aesenclast">
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¶
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</a></h3>
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<pre>STATE := SRC1;
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RoundKey := SRC2;
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STATE := ShiftRows( STATE );
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STATE := SubBytes( STATE );
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DEST[127:0] := STATE XOR RoundKey;
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vaesenclast--128b-and-256b-vex-encoded-versions-">VAESENCLAST (128b and 256b VEX Encoded Versions)<a class="anchor" href="#vaesenclast--128b-and-256b-vex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (1,128), (2,256)
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FOR I=0 to KL-1:
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STATE := SRC1.xmm[i]
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RoundKey := SRC2.xmm[i]
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STATE := ShiftRows( STATE )
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STATE := SubBytes( STATE )
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DEST.xmm[i] := STATE XOR RoundKey
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vaesenclast--evex-encoded-version-">VAESENCLAST (EVEX Encoded Version)<a class="anchor" href="#vaesenclast--evex-encoded-version-">
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¶
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</a></h3>
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<pre>(KL,VL) = (1,128), (2,256), (4,512)
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FOR i = 0 to KL-1:
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STATE := SRC1.xmm[i]
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RoundKey := SRC2.xmm[i]
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STATE := ShiftRows( STATE )
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STATE := SubBytes( STATE )
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DEST.xmm[i] := STATE XOR RoundKey
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>(V)AESENCLAST __m128i _mm_aesenclast (__m128i, __m128i)
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</pre>
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<pre>VAESENCLAST __m256i _mm256_aesenclast_epi128(__m256i, __m256i);
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</pre>
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<pre>VAESENCLAST __m512i _mm512_aesenclast_epi128(__m512i, __m512i);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded: See <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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