107 lines
6.4 KiB
HTML
107 lines
6.4 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>WRMSR
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— Write to Model Specific Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>WRMSR
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— Write to Model Specific Register</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 30</td>
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<td>WRMSR</td>
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<td>ZO</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Write the value in EDX:EAX to MSR specified by ECX.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously read.</p>
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<p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to bits in a reserved MSR.</p>
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<p>When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see “Translation Lookaside Buffers (TLBs)” in Chapter 3 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).</p>
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<p>MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Chapter 2, “Model-Specific Registers (MSRs),” of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 4, lists all MSRs that can be written with this instruction and their addresses. Note that each processor family has its own set of MSRs.</p>
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<p>The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 9 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.</p>
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<p>The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before using this instruction.</p>
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<h2 id="ia-32-architecture-compatibility">IA-32 Architecture Compatibility<a class="anchor" href="#ia-32-architecture-compatibility">
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¶
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</a></h2>
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<p>The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>MSR[ECX] := EDX:EAX;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If the current privilege level is not 0.</td></tr>
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<tr>
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<td>If the value in ECX specifies a reserved or unimplemented MSR address.</td></tr>
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<tr>
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<td>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</td></tr>
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<tr>
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<td>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_L-STAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="3">#GP</td>
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<td>If the value in ECX specifies a reserved or unimplemented MSR address.</td></tr>
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<tr>
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<td>If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.</td></tr>
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<tr>
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<td>If the source register contains a non-canonical address and ECX specifies one of the following MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_L-STAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>The WRMSR instruction is not recognized in virtual-8086 mode.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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