125 lines
4.9 KiB
HTML
125 lines
4.9 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>WRFSBASE/WRGSBASE
|
||
— Write FS/GS Segment Base</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>WRFSBASE/WRGSBASE
|
||
— Write FS/GS Segment Base</h1>
|
||
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32-bit Mode</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>F3 0F AE /2 WRFSBASE r32</td>
|
||
<td>M</td>
|
||
<td>V/I</td>
|
||
<td>FSGSBASE</td>
|
||
<td>Load the FS base address with the 32-bit value in the source register.</td></tr>
|
||
<tr>
|
||
<td>F3 REX.W 0F AE /2 WRFSBASE r64</td>
|
||
<td>M</td>
|
||
<td>V/I</td>
|
||
<td>FSGSBASE</td>
|
||
<td>Load the FS base address with the 64-bit value in the source register.</td></tr>
|
||
<tr>
|
||
<td>F3 0F AE /3 WRGSBASE r32</td>
|
||
<td>M</td>
|
||
<td>V/I</td>
|
||
<td>FSGSBASE</td>
|
||
<td>Load the GS base address with the 32-bit value in the source register.</td></tr>
|
||
<tr>
|
||
<td>F3 REX.W 0F AE /3 WRGSBASE r64</td>
|
||
<td>M</td>
|
||
<td>V/I</td>
|
||
<td>FSGSBASE</td>
|
||
<td>Load the GS base address with the 64-bit value in the source register.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>M</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Loads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.</p>
|
||
<p>The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source register are ignored and upper 32 bits of the base address (for FS or GS) are cleared.</p>
|
||
<p>This instruction is supported only in 64-bit mode.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<pre>FS/GS segment base address := SRC;
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 id="c-c++-compiler-intrinsic-equivalent">C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>WRFSBASE void _writefsbase_u32( unsigned int );
|
||
</pre>
|
||
<pre>WRFSBASE _writefsbase_u64( unsigned __int64 );
|
||
</pre>
|
||
<pre>WRGSBASE void _writegsbase_u32( unsigned int );
|
||
</pre>
|
||
<pre>WRGSBASE _writegsbase_u64( unsigned __int64 );
|
||
</pre>
|
||
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The WRFSBASE and WRGSBASE instructions are not recognized in protected mode.</td></tr></table>
|
||
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.</td></tr></table>
|
||
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.</td></tr></table>
|
||
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>The WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.</td></tr></table>
|
||
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="3">#UD</td>
|
||
<td>If the LOCK prefix is used.</td></tr>
|
||
<tr>
|
||
<td>If CR4.FSGSBASE[bit 16] = 0.</td></tr>
|
||
<tr>
|
||
<td>If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0</td></tr>
|
||
<tr>
|
||
<td>#GP(0)</td>
|
||
<td>If the source register contains a non-canonical address.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|