145 lines
6.6 KiB
HTML
145 lines
6.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPDPWSSD
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— Multiply and Add Signed Word Integers</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPDPWSSD
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— Multiply and Add Signed Word Integers</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1, xmm2, xmm3/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX-VNNI</td>
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<td>Multiply groups of 2 pairs signed words in xmm3/m128 with corresponding signed words of xmm2, summing those products and adding them to doubleword result in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 52 /r VPDPWSSD ymm1, ymm2, ymm3/m256</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX-VNNI</td>
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<td>Multiply groups of 2 pairs signed words in ymm3/m256 with corresponding signed words of ymm2, summing those products and adding them to doubleword result in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512_VNNI AVX512VL</td>
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<td>Multiply groups of 2 pairs signed words in xmm3/m128/m32bcst with corresponding signed words of xmm2, summing those products and adding them to doubleword result in xmm1, under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 52 /r VPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512_VNNI AVX512VL</td>
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<td>Multiply groups of 2 pairs signed words in ymm3/m256/m32bcst with corresponding signed words of ymm2, summing those products and adding them to doubleword result in ymm1, under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 52 /r VPDPWSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512_VNNI</td>
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<td>Multiply groups of 2 pairs signed words in zmm3/m512/m32bcst with corresponding signed words of zmm2, summing those products and adding them to doubleword result in zmm1, under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Full</td>
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<td>ModRM:reg (r, w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.</p>
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<p>This instruction supports memory fault suppression.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vpdpwssd-dest--src1--src2--vex-encoded-versions-">VPDPWSSD dest, src1, src2 (VEX encoded versions)<a class="anchor" href="#vpdpwssd-dest--src1--src2--vex-encoded-versions-">
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¶
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</a></h4>
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<pre>VL=(128, 256)
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KL=VL/32
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ORIGDEST := DEST
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FOR i := 0 TO KL-1:
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p1dword := SIGN_EXTEND(SRC1.word[2*i+0]) * SIGN_EXTEND(SRC2.word[2*i+0] )
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p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(SRC2.word[2*i+1] )
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DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dword
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DEST[MAX_VL-1:VL] := 0
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</pre>
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<h4 id="vpdpwssd-dest--src1--src2--evex-encoded-versions-">VPDPWSSD dest, src1, src2 (EVEX encoded versions)<a class="anchor" href="#vpdpwssd-dest--src1--src2--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL,VL)=(4,128), (8,256), (16,512)
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ORIGDEST := DEST
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FOR i := 0 TO KL-1:
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IF k1[i] or *no writemask*:
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IF SRC2 is memory and EVEX.b == 1:
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t := SRC2.dword[0]
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ELSE:
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t := SRC2.dword[i]
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p1dword := SIGN_EXTEND(SRC1.word[2*i]) * SIGN_EXTEND(t.word[0])
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p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(t.word[1])
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DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dword
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ELSE IF *zeroing*:
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DEST.dword[i] := 0
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ELSE: // Merge masking, dest element unchanged
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DEST.dword[i] := ORIGDEST.dword[i]
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DEST[MAX_VL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VPDPWSSD __m128i _mm_dpwssd_avx_epi32(__m128i, __m128i, __m128i);
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</pre>
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<pre>VPDPWSSD __m128i _mm_dpwssd_epi32(__m128i, __m128i, __m128i);
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</pre>
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<pre>VPDPWSSD __m128i _mm_mask_dpwssd_epi32(__m128i, __mmask8, __m128i, __m128i);
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</pre>
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<pre>VPDPWSSD __m128i _mm_maskz_dpwssd_epi32(__mmask8, __m128i, __m128i, __m128i);
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</pre>
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<pre>VPDPWSSD __m256i _mm256_dpwssd_avx_epi32(__m256i, __m256i, __m256i);
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</pre>
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<pre>VPDPWSSD __m256i _mm256_dpwssd_epi32(__m256i, __m256i, __m256i);
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</pre>
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<pre>VPDPWSSD __m256i _mm256_mask_dpwssd_epi32(__m256i, __mmask8, __m256i, __m256i);
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</pre>
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<pre>VPDPWSSD __m256i _mm256_maskz_dpwssd_epi32(__mmask8, __m256i, __m256i, __m256i);
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</pre>
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<pre>VPDPWSSD __m512i _mm512_dpwssd_epi32(__m512i, __m512i, __m512i);
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</pre>
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<pre>VPDPWSSD __m512i _mm512_mask_dpwssd_epi32(__m512i, __mmask16, __m512i, __m512i);
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</pre>
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<pre>VPDPWSSD __m512i _mm512_maskz_dpwssd_epi32(__mmask16, __m512i, __m512i, __m512i);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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