924 lines
76 KiB
HTML
924 lines
76 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPBROADCAST
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— Load Integer and Broadcast</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPBROADCAST
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— Load Integer and Broadcast</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 78 /r VPBROADCASTB xmm1, xmm2/m8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a byte integer in the source operand to sixteen locations in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 78 /r VPBROADCASTB ymm1, xmm2/m8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a byte integer in the source operand to thirty-two locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 78 /r VPBROADCASTB xmm1{k1}{z}, xmm2/m8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Broadcast a byte integer in the source operand to locations in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 78 /r VPBROADCASTB ymm1{k1}{z}, xmm2/m8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Broadcast a byte integer in the source operand to locations in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 78 /r VPBROADCASTB zmm1{k1}{z}, xmm2/m8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Broadcast a byte integer in the source operand to 64 locations in zmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 79 /r VPBROADCASTW xmm1, xmm2/m16</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a word integer in the source operand to eight locations in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 79 /r VPBROADCASTW ymm1, xmm2/m16</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a word integer in the source operand to sixteen locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 79 /r VPBROADCASTW xmm1{k1}{z}, xmm2/m16</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Broadcast a word integer in the source operand to locations in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 79 /r VPBROADCASTW ymm1{k1}{z}, xmm2/m16</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Broadcast a word integer in the source operand to locations in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 79 /r VPBROADCASTW zmm1{k1}{z}, xmm2/m16</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Broadcast a word integer in the source operand to 32 locations in zmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 58 /r VPBROADCASTD xmm1, xmm2/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a dword integer in the source operand to four locations in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 58 /r VPBROADCASTD ymm1, xmm2/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a dword integer in the source operand to eight locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 58 /r VPBROADCASTD xmm1 {k1}{z}, xmm2/m32</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Broadcast a dword integer in the source operand to locations in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 58 /r VPBROADCASTD ymm1 {k1}{z}, xmm2/m32</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Broadcast a dword integer in the source operand to locations in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 58 /r VPBROADCASTD zmm1 {k1}{z}, xmm2/m32</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Broadcast a dword integer in the source operand to locations in zmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 59 /r VPBROADCASTQ xmm1, xmm2/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a qword element in source operand to two locations in xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 59 /r VPBROADCASTQ ymm1, xmm2/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast a qword element in source operand to four locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W1 59 /r VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Broadcast a qword element in source operand to locations in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W1 59 /r VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Broadcast a qword element in source operand to locations in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 59 /r VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Broadcast a qword element in source operand to locations in zmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 59 /r VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Broadcast two dword elements in source operand to locations in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 59 /r VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Broadcast two dword elements in source operand to locations in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 59 /r VBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Broadcast two dword elements in source operand to locations in zmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 5A /r VBROADCASTI128 ymm1, m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Broadcast 128 bits of integer data in mem to low and high 128-bits in ymm1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 5A /r VBROADCASTI32X4 ymm1 {k1}{z}, m128</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Broadcast 128 bits of 4 doubleword integer data in mem to locations in ymm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 5A /r VBROADCASTI32X4 zmm1 {k1}{z}, m128</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Broadcast 128 bits of 4 doubleword integer data in mem to locations in zmm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W1 5A /r VBROADCASTI64X2 ymm1 {k1}{z}, m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Broadcast 128 bits of 2 quadword integer data in mem to locations in ymm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 5A /r VBROADCASTI64X2 zmm1 {k1}{z}, m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Broadcast 128 bits of 2 quadword integer data in mem to locations in zmm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 5B /r VBROADCASTI32X8 zmm1 {k1}{z}, m256</td>
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<td>E</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Broadcast 256 bits of 8 doubleword integer data in mem to locations in zmm1 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 5B /r VBROADCASTI64X4 zmm1 {k1}{z}, m256</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Broadcast 256 bits of 4 quadword integer data in mem to locations in zmm1 using writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple2</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Tuple4</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>E</td>
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<td>Tuple8</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Load integer data from the source operand (the second operand) and broadcast to all elements of the destination operand (the first operand).</p>
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<p>VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register. VPBROAD-CASTI128 support the source operand of 128-bit memory location. Register source encodings for VPBROADCAS-TI128 is reserved and will #UD. Bits (MAXVL-1:256) of the destination register are zeroed.</p>
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<p>EVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64-bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the writemask k1.</p>
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<p>VPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>If VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.</p>
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<figure id="fig-5-16">
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<figcaption><a href='vpbroadcast.html#fig-5-16'>Figure 5-16</a>. VPBROADCASTD Operation (VEX.256 encoded version)</figcaption></figure>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416799999998pt; fill: #000" textLength="9.172166699999991" x="321.24" y="104.4908978">X0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416799999998pt; fill: #000" textLength="9.232485099999963" x="395.52" y="104.4908978">X0</text></g></svg>
|
||
<figcaption><a href='vpbroadcast.html#fig-5-18'>Figure 5-18</a>. VPBROADCASTQ Operation (256-bit version)</figcaption></figure>
|
||
<figure id="fig-5-19">
|
||
<svg style="width: 475.77604799999995pt; height: 126.93597599999988pt" viewBox="101.24000000000001 0.0 401.48004 110.77997999999991">
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<rect height="0.48004" style="fill: rgb(0%, 0%, 0%)" width="148.74" x="146.4" y="77.5199399999999"></rect>
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<rect height="0.48004" style="fill: rgb(0%, 0%, 0%)" width="148.74" x="146.16" y="91.07993999999997"></rect>
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<rect height="13.8" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="146.16" y="77.51997999999992"></rect>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="18.768824139999936" x="270.59898748" y="33.57118173999993">m128</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.172166699999991" x="354.96" y="35.19087779999995">X0</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="20.024954820000005" x="126.72" y="87.93087779999996">DEST</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.17216670000002" x="207.12" y="89.55087779999997">X0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.172166699999991" x="355.62" y="89.55087779999997">X0</text></g></svg>
|
||
<figcaption><a href='vpbroadcast.html#fig-5-19'>Figure 5-19</a>. VBROADCASTI128 Operation (256-bit version)</figcaption></figure>
|
||
<figure id="fig-5-20">
|
||
<svg style="width: 475.77604799999995pt; height: 126.143976pt" viewBox="101.24000000000001 0.0 401.48004 110.11998">
|
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<g xmlns="http://www.w3.org/2000/svg" style="fill: none; stroke: none">
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<rect height="104.16" style="fill: rgb(0%, 0%, 0%)" width="0.48" x="103.74000000000001" y="0.479979999999955"></rect>
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<rect height="104.16" style="fill: rgb(0%, 0%, 0%)" width="0.48004" x="499.74" y="0.479979999999955"></rect>
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<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="396.48" x="103.74000000000001" y="104.63997"></rect>
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<rect height="1.02" style="fill: rgb(0%, 0%, 0%)" width="4.32" x="358.08" y="59.21998000000002"></rect>
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<rect height="0.48001000000000005" style="fill: rgb(0%, 0%, 0%)" width="148.74" x="146.16" y="89.75997000000001"></rect>
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<rect height="13.74" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="146.16" y="76.25997999999998"></rect>
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|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.172166699999991" x="352.98" y="34.530877799999985">X0</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="20.024954820000005" x="126.72" y="86.61087779999997">DEST</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.17216670000002" x="207.12" y="88.23087779999997">X0</text>
|
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.414416800000026pt; fill: #000" textLength="9.172166699999991" x="355.62" y="88.23087779999997">X0</text></g></svg>
|
||
<figcaption><a href='vpbroadcast.html#fig-5-20'>Figure 5-20</a>. VBROADCASTI256 Operation (512-bit version)</figcaption></figure>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="vpbroadcastb--evex-encoded-versions-">VPBROADCASTB (EVEX encoded versions)<a class="anchor" href="#vpbroadcastb--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 8
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+7:i] := SRC[7:0]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+7:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+7:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vpbroadcastw--evex-encoded-versions-">VPBROADCASTW (EVEX encoded versions)<a class="anchor" href="#vpbroadcastw--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 16
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+15:i] := SRC[15:0]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+15:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+15:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vpbroadcastd--128-bit-version-">VPBROADCASTD (128 bit version)<a class="anchor" href="#vpbroadcastd--128-bit-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>temp := SRC[31:0]
|
||
DEST[31:0] := temp
|
||
DEST[63:32] := temp
|
||
DEST[95:64] := temp
|
||
DEST[127:96] := temp
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h4 id="vpbroadcastd--vex-256-encoded-version-">VPBROADCASTD (VEX.256 encoded version)<a class="anchor" href="#vpbroadcastd--vex-256-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>temp := SRC[31:0]
|
||
DEST[31:0] := temp
|
||
DEST[63:32] := temp
|
||
DEST[95:64] := temp
|
||
DEST[127:96] := temp
|
||
DEST[159:128] := temp
|
||
DEST[191:160] := temp
|
||
DEST[223:192] := temp
|
||
DEST[255:224] := temp
|
||
DEST[MAXVL-1:256] := 0
|
||
VPBROADCASTD (EVEX encoded versions)
|
||
(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := SRC[31:0]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vpbroadcastq--vex-256-encoded-version-">VPBROADCASTQ (VEX.256 encoded version)<a class="anchor" href="#vpbroadcastq--vex-256-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>temp := SRC[63:0]
|
||
DEST[63:0] := temp
|
||
DEST[127:64] := temp
|
||
DEST[191:128] := temp
|
||
DEST[255:192] := temp
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h4 id="vpbroadcastq--evex-encoded-versions-">VPBROADCASTQ (EVEX encoded versions)<a class="anchor" href="#vpbroadcastq--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+63:i] := SRC[63:0]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
VBROADCASTI32x2 (EVEX encoded versions)
|
||
(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
n := (j mod 2) * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := SRC[n+31:n]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vbroadcasti128--vex-256-encoded-version-">VBROADCASTI128 (VEX.256 encoded version)<a class="anchor" href="#vbroadcasti128--vex-256-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>temp := SRC[127:0]
|
||
DEST[127:0] := temp
|
||
DEST[255:128] := temp
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h4 id="vbroadcasti32x4--evex-encoded-versions-">VBROADCASTI32X4 (EVEX encoded versions)<a class="anchor" href="#vbroadcasti32x4--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j* 32
|
||
n := (j modulo 4) * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := SRC[n+31:n]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vbroadcasti64x2--evex-encoded-versions-">VBROADCASTI64X2 (EVEX encoded versions)<a class="anchor" href="#vbroadcasti64x2--evex-encoded-versions-">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
n := (j modulo 2) * 64
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+63:i] := SRC[n+63:n]
|
||
ELSE
|
||
IF *merging-masking*
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] = 0
|
||
FI
|
||
FI;
|
||
ENDFOR;
|
||
</pre>
|
||
<h4 id="vbroadcasti32x8--evex-u1-512-encoded-version-">VBROADCASTI32X8 (EVEX.U1.512 encoded version)<a class="anchor" href="#vbroadcasti32x8--evex-u1-512-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>FOR j := 0 TO 15
|
||
i := j * 32
|
||
n := (j modulo 8) * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+31:i] := SRC[n+31:n]
|
||
ELSE
|
||
IF *merging-masking*
|
||
; merging-masking
|
||
THEN *DEST[i+31:i] remains unchanged*
|
||
ELSE
|
||
; zeroing-masking
|
||
DEST[i+31:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vbroadcasti64x4--evex-512-encoded-version-">VBROADCASTI64X4 (EVEX.512 encoded version)<a class="anchor" href="#vbroadcasti64x4--evex-512-encoded-version-">
|
||
¶
|
||
</a></h4>
|
||
<pre>FOR j := 0 TO 7
|
||
i := j * 64
|
||
n := (j modulo 4) * 64
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+63:i] := SRC[n+63:n]
|
||
ELSE
|
||
IF *merging-masking*
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m128i _mm_broadcast_i32x2(__m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m128i _mm_mask_broadcast_i32x2(__m128i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x2 __m128i _mm_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);
|
||
</pre>
|
||
<pre>VBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);
|
||
</pre>
|
||
<pre>VBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-23</span>, “Type 6 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded instructions, syntax with reg/mem operand, see <span class="not-imported">Table 2-53</span>, “Type E6 Class Exception Conditions.”</p>
|
||
<p>Additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="3">#UD</td>
|
||
<td>If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.</td></tr>
|
||
<tr>
|
||
<td>If EVEX.L’L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.</td></tr>
|
||
<tr>
|
||
<td>If EVEX.L’L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|