129 lines
5.7 KiB
HTML
129 lines
5.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VMULPH
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— Multiply Packed FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VMULPH
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— Multiply Packed FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En bit Mode Flag
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Support Instruction En bit Mode Flag
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Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.NP.MAP5.W0 59 /r VMULPH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Multiply packed FP16 values from xmm3/m128/m16bcst to xmm2 and store the result in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.NP.MAP5.W0 59 /r VMULPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Multiply packed FP16 values from ymm3/m256/m16bcst to ymm2 and store the result in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.NP.MAP5.W0 59 /r VMULPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Multiply packed FP16 values in zmm3/m512/m16bcst with zmm2 and store the result in zmm1 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction multiplies packed FP16 values from source operands and stores the packed FP16 result in the destination operand. The destination elements are updated according to the writemask.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vmulph--evex-encoded-versions--when-src2-operand-is-a-register">VMULPH (EVEX encoded versions) when src2 operand is a register<a class="anchor" href="#vmulph--evex-encoded-versions--when-src2-operand-is-a-register">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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IF (VL = 512) AND (EVEX.b = 1):
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SET_RM(EVEX.RC)
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ELSE
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SET_RM(MXCSR.RC)
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FOR j := 0 TO KL-1:
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IF k1[j] OR *no writemask*:
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DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
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ELSE IF *zeroing*:
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DEST.fp16[j] := 0
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// else dest.fp16[j] remains unchanged
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="vmulph--evex-encoded-versions--when-src2-operand-is-a-memory-source">VMULPH (EVEX encoded versions) when src2 operand is a memory source<a class="anchor" href="#vmulph--evex-encoded-versions--when-src2-operand-is-a-memory-source">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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FOR j := 0 TO KL-1:
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IF k1[j] OR *no writemask*:
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IF EVEX.b = 1:
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DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[0]
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ELSE:
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DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
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ELSE IF *zeroing*:
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DEST.fp16[j] := 0
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// else dest.fp16[j] remains unchanged
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VMULPH __m128h _mm_mask_mul_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);
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</pre>
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<pre>VMULPH __m128h _mm_maskz_mul_ph (__mmask8 k, __m128h a, __m128h b);
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</pre>
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<pre>VMULPH __m128h _mm_mul_ph (__m128h a, __m128h b);
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</pre>
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<pre>VMULPH __m256h _mm256_mask_mul_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);
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</pre>
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<pre>VMULPH __m256h _mm256_maskz_mul_ph (__mmask16 k, __m256h a, __m256h b);
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</pre>
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<pre>VMULPH __m256h _mm256_mul_ph (__m256h a, __m256h b);
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</pre>
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<pre>VMULPH __m512h _mm512_mask_mul_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);
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</pre>
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<pre>VMULPH __m512h _mm512_maskz_mul_ph (__mmask32 k, __m512h a, __m512h b);
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</pre>
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<pre>VMULPH __m512h _mm512_mul_ph (__m512h a, __m512h b);
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</pre>
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<pre>VMULPH __m512h _mm512_mask_mul_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);
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</pre>
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<pre>VMULPH __m512h _mm512_maskz_mul_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);
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</pre>
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<pre>VMULPH __m512h _mm512_mul_round_ph (__m512h a, __m512h b, int rounding);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Underflow, Overflow, Precision, Denormal</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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