163 lines
6.9 KiB
HTML
163 lines
6.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>SMSW
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— Store Machine Status Word</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>SMSW
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— Store Machine Status Word</h1>
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<table>
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<tr>
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<th>Opcode*</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 01 /4</td>
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<td>SMSW r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Store machine status word to r/m16.</td></tr>
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<tr>
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<td>0F 01 /4</td>
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<td>SMSW r32/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Store machine status word in low-order 16 bits of r32/m16; high-order 16 bits of r32 are undefined.</td></tr>
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<tr>
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<td>REX.W + 0F 01 /4</td>
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<td>SMSW r64/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Store machine status word in low-order 16 bits of r64/m16; high-order 16 bits of r32 are undefined.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (w)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The destination operand can be a general-purpose register or a memory location.</p>
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<p>In non-64-bit modes, when the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are copied into the low-order 16 bits of the register and the high-order 16 bits are undefined. When the destination operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity, regardless of the operand size.</p>
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<p>In 64-bit mode, the behavior of the SMSW instruction is defined by the following examples:</p>
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<ul>
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<li>SMSW r16 operand size 16, store CR0[15:0] in r16</li>
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<li>SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32</li>
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<li>SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64</li>
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<li>SMSW m16 operand size 16, store CR0[15:0] in m16</li>
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<li>SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)</li>
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<li>SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)</li></ul>
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<p>SMSW is only useful in operating-system software. However, it is not a privileged instruction and can be used in application programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and procedures intended to run on IA-32 and Intel 64 processors beginning with the Intel386 processors should use the MOV CR instruction to load the machine status word.</p>
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<p>See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 26 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST := CR0[15:0];
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(* Machine status word *)
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If the destination is located in a non-writable segment.</td></tr>
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<tr>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</td></tr>
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<tr>
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<td>If CR4.UMIP = 1 and CPL > 0.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If CR4.UMIP = 1.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>If CR4.UMIP = 1 and CPL > 0.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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