122 lines
4.8 KiB
HTML
122 lines
4.8 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>RDFSBASE/RDGSBASE
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— Read FS/GS Segment Base</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>RDFSBASE/RDGSBASE
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— Read FS/GS Segment Base</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F3 0F AE /0 RDFSBASE r32</td>
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<td>M</td>
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<td>V/I</td>
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<td>FSGSBASE</td>
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<td>Load the 32-bit destination register with the FS base address.</td></tr>
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<tr>
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<td>F3 REX.W 0F AE /0 RDFSBASE r64</td>
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<td>M</td>
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<td>V/I</td>
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<td>FSGSBASE</td>
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<td>Load the 64-bit destination register with the FS base address.</td></tr>
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<tr>
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<td>F3 0F AE /1 RDGSBASE r32</td>
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<td>M</td>
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<td>V/I</td>
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<td>FSGSBASE</td>
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<td>Load the 32-bit destination register with the GS base address.</td></tr>
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<tr>
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<td>F3 REX.W 0F AE /1 RDGSBASE r64</td>
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<td>M</td>
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<td>V/I</td>
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<td>FSGSBASE</td>
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<td>Load the 64-bit destination register with the GS base address.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (w)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Loads the general-purpose register indicated by the ModR/M:r/m field with the FS or GS segment base address.</p>
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<p>The destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source base address (for FS or GS) are ignored and upper 32 bits of the destination register are cleared.</p>
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<p>This instruction is supported only in 64-bit mode.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST := FS/GS segment base address;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="c-c++-compiler-intrinsic-equivalent">C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>RDFSBASE unsigned int _readfsbase_u32(void );
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</pre>
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<pre>RDFSBASE unsigned __int64 _readfsbase_u64(void );
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</pre>
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<pre>RDGSBASE unsigned int _readgsbase_u32(void );
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</pre>
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<pre>RDGSBASE unsigned __int64 _readgsbase_u64(void );
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</pre>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The RDFSBASE and RDGSBASE instructions are not recognized in protected mode.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The RDFSBASE and RDGSBASE instructions are not recognized in real-address mode.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The RDFSBASE and RDGSBASE instructions are not recognized in virtual-8086 mode.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>The RDFSBASE and RDGSBASE instructions are not recognized in compatibility mode.</td></tr></table>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CR4.FSGSBASE[bit 16] = 0.</td></tr>
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<tr>
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<td>If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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