120 lines
5.2 KiB
HTML
120 lines
5.2 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PTEST
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— Logical Compare</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PTEST
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— Logical Compare</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 17 /r PTEST xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Set ZF if xmm2/m128 AND xmm1 result is all 0s. Set CF if xmm2/m128 AND NOT xmm1 result is all 0s.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 17 /r VPTEST xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Set ZF and CF depending on bitwise AND and ANDN of sources.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 17 /r VPTEST ymm1, ymm2/m256</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Set ZF and CF depending on bitwise AND and ANDN of sources.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first operand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of the bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand.</p>
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<p>The first source register is specified by the ModR/M <em>reg</em> field.</p>
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<p>128-bit versions: The first source register is an XMM register. The second source register can be an XMM register or a 128-bit memory location. The destination register is not modified.</p>
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<p>VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM register or a 256-bit memory location. The destination register is not modified.</p>
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<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="-v-ptest--128-bit-version-">(V)PTEST (128-bit Version)<a class="anchor" href="#-v-ptest--128-bit-version-">
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¶
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</a></h3>
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<pre>IF (SRC[127:0] BITWISE AND DEST[127:0] = 0)
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THEN ZF := 1;
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ELSE ZF := 0;
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IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)
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THEN CF := 1;
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ELSE CF := 0;
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DEST (unmodified)
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AF := OF := PF := SF := 0;
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</pre>
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<h3 id="vptest--vex-256-encoded-version-">VPTEST (VEX.256 Encoded Version)<a class="anchor" href="#vptest--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF := 1;
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ELSE ZF := 0;
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IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF := 1;
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ELSE CF := 0;
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DEST (unmodified)
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AF := OF := PF := SF := 0;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>PTEST int _mm_testz_si128 (__m128i s1, __m128i s2);
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</pre>
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<pre>PTEST int _mm_testc_si128 (__m128i s1, __m128i s2);
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</pre>
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<pre>PTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2);
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</pre>
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<pre>VPTEST int _mm256_testz_si256 (__m256i s1, __m256i s2);
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</pre>
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<pre>VPTEST int _mm256_testc_si256 (__m256i s1, __m256i s2);
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</pre>
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<pre>VPTEST int _mm256_testnzc_si256 (__m256i s1, __m256i s2);
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</pre>
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<pre>VPTEST int _mm_testz_si128 (__m128i s1, __m128i s2);
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</pre>
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<pre>VPTEST int _mm_testc_si128 (__m128i s1, __m128i s2);
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</pre>
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<pre>VPTEST int _mm_testnzc_si128 (__m128i s1, __m128i s2);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>The OF, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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