186 lines
9.9 KiB
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186 lines
9.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PMADDUBSW
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— Multiply and Add Packed Signed and Unsigned Bytes</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PMADDUBSW
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— Multiply and Add Packed Signed and Unsigned Bytes</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 38 04 /r<sup>1</sup> PMADDUBSW mm1, mm2/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to mm1.</td></tr>
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<tr>
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<td>66 0F 38 04 /r PMADDUBSW xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 04 /r VPMADDUBSW xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 04 /r VPMADDUBSW ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to ymm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.WIG 04 /r VPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.WIG 04 /r VPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to ymm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.WIG 04 /r VPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to zmm1 under writemask k1.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corresponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example, the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same operation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
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<p>In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15.</p>
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<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.</p>
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<p>VEX.128 and EVEX.128 encoded versions: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
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<p>VEX.256 and EVEX.256 encoded versions: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.</p>
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<p>EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The first source and destination operands are ZMM registers.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="pmaddubsw--with-64-bit-operands-">PMADDUBSW (With 64-bit Operands)<a class="anchor" href="#pmaddubsw--with-64-bit-operands-">
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¶
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</a></h3>
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<pre>DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
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DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
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DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
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DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);
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</pre>
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<h3 id="pmaddubsw--with-128-bit-operands-">PMADDUBSW (With 128-bit Operands)<a class="anchor" href="#pmaddubsw--with-128-bit-operands-">
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¶
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</a></h3>
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<pre>DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
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// Repeat operation for 2nd through 7th word
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SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);
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</pre>
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<h3 id="vpmaddubsw--vex-128-encoded-version-">VPMADDUBSW (VEX.128 Encoded Version)<a class="anchor" href="#vpmaddubsw--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[15:0] := SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
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// Repeat operation for 2nd through 7th word
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DEST[127:112] := SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vpmaddubsw--vex-256-encoded-version-">VPMADDUBSW (VEX.256 Encoded Version)<a class="anchor" href="#vpmaddubsw--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[15:0] := SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
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// Repeat operation for 2nd through 15th word
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DEST[255:240] := SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpmaddubsw--evex-encoded-versions-">VPMADDUBSW (EVEX Encoded Versions)<a class="anchor" href="#vpmaddubsw--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := SaturateToSignedWord(SRC2[i+15:i+8]* SRC1[i+15:i+8] + SRC2[i+7:i]*SRC1[i+7:i])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+15:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+15:i] = 0
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FI
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
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¶
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</a></h2>
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<pre>VPMADDUBSW __m512i _mm512_maddubs_epi16( __m512i a, __m512i b);
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</pre>
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<pre>VPMADDUBSW __m512i _mm512_mask_maddubs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMADDUBSW __m512i _mm512_maskz_maddubs_epi16( __mmask32 k, __m512i a, __m512i b);
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</pre>
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<pre>VPMADDUBSW __m256i _mm256_mask_maddubs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMADDUBSW __m256i _mm256_maskz_maddubs_epi16( __mmask16 k, __m256i a, __m256i b);
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</pre>
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<pre>VPMADDUBSW __m128i _mm_mask_maddubs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>VPMADDUBSW __m128i _mm_maskz_maddubs_epi16( __mmask8 k, __m128i a, __m128i b);
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</pre>
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<pre>PMADDUBSW __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
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</pre>
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<pre>(V)PMADDUBSW __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
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</pre>
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<pre>VPMADDUBSW __m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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