200 lines
8.4 KiB
HTML
200 lines
8.4 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVQ
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— Move Quadword</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVQ
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— Move Quadword</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/ En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 6F /r MOVQ mm, mm/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Move quadword from mm/m64 to mm.</td></tr>
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<tr>
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<td>NP 0F 7F /r MOVQ mm/m64, mm</td>
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<td>B</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Move quadword from mm to mm/m64.</td></tr>
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<tr>
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<td>F3 0F 7E /r MOVQ xmm1, xmm2/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move quadword from xmm2/mem64 to xmm1.</td></tr>
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<tr>
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<td>VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1, xmm2/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move quadword from xmm2 to xmm1.</td></tr>
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<tr>
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<td>EVEX.128.F3.0F.W1 7E /r VMOVQ xmm1, xmm2/m64</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move quadword from xmm2/m64 to xmm1.</td></tr>
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<tr>
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<td>66 0F D6 /r MOVQ xmm2/m64, xmm1</td>
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<td>B</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move quadword from xmm1 to xmm2/mem64.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG D6 /r VMOVQ xmm1/m64, xmm2</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move quadword from xmm2 register to xmm1/m64.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 D6 /r VMOVQ xmm1/m64, xmm2</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move quadword from xmm2 register to xmm1/m64.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Copies a quadword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations. This instruction can be used to move a quadword between two MMX technology registers or between an MMX technology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.</p>
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<p>When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.</p>
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<p>In 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<p>If VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="movq-instruction-when-operating-on-mmx-technology-registers-and-memory-locations">MOVQ Instruction When Operating on MMX Technology Registers and Memory Locations<a class="anchor" href="#movq-instruction-when-operating-on-mmx-technology-registers-and-memory-locations">
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¶
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</a></h3>
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<pre>DEST := SRC;
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</pre>
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<h3 id="movq-instruction-when-source-and-destination-operands-are-xmm-registers">MOVQ Instruction When Source and Destination Operands are XMM Registers<a class="anchor" href="#movq-instruction-when-source-and-destination-operands-are-xmm-registers">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0];
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DEST[127:64] := 0000000000000000H;
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</pre>
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<h3 id="movq-instruction-when-source-operand-is-xmm-register-and-destination">MOVQ Instruction When Source Operand is XMM Register and Destination<a class="anchor" href="#movq-instruction-when-source-operand-is-xmm-register-and-destination">
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¶
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</a></h3>
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<pre>operand is memory location:
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DEST := SRC[63:0];
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</pre>
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<h3 id="movq-instruction-when-source-operand-is-memory-location-and-destination">MOVQ Instruction When Source Operand is Memory Location and Destination<a class="anchor" href="#movq-instruction-when-source-operand-is-memory-location-and-destination">
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¶
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</a></h3>
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<pre>operand is XMM register:
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DEST[63:0] := SRC;
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DEST[127:64] := 0000000000000000H;
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</pre>
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<h3 id="vmovq--vex-128-f3-0f-7e--with-xmm-register-source-and-destination">VMOVQ (VEX.128.F3.0F 7E) With XMM Register Source and Destination<a class="anchor" href="#vmovq--vex-128-f3-0f-7e--with-xmm-register-source-and-destination">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--vex-128-66-0f-d6--with-xmm-register-source-and-destination">VMOVQ (VEX.128.66.0F D6) With XMM Register Source and Destination<a class="anchor" href="#vmovq--vex-128-66-0f-d6--with-xmm-register-source-and-destination">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--7e---evex-encoded-version--with-xmm-register-source-and-destination">VMOVQ (7E - EVEX Encoded Version) With XMM Register Source and Destination<a class="anchor" href="#vmovq--7e---evex-encoded-version--with-xmm-register-source-and-destination">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--d6---evex-encoded-version--with-xmm-register-source-and-destination">VMOVQ (D6 - EVEX Encoded Version) With XMM Register Source and Destination<a class="anchor" href="#vmovq--d6---evex-encoded-version--with-xmm-register-source-and-destination">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--7e--with-memory-source">VMOVQ (7E) With Memory Source<a class="anchor" href="#vmovq--7e--with-memory-source">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--7e---evex-encoded-version--with-memory-source">VMOVQ (7E - EVEX Encoded Version) With Memory Source<a class="anchor" href="#vmovq--7e---evex-encoded-version--with-memory-source">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[63:0]
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DEST[:MAXVL-1:64] := 0
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</pre>
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<h3 id="vmovq--d6--with-memory-dest">VMOVQ (D6) With Memory DEST<a class="anchor" href="#vmovq--d6--with-memory-dest">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC2[63:0]
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VMOVQ __m128i _mm_loadu_si64( void * s);
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</pre>
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<pre>VMOVQ void _mm_storeu_si64( void * d, __m128i s);
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</pre>
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<pre>MOVQ m128i _mm_move_epi64(__m128i a)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 23-8</span>, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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