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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>CVTTSD2SI
— Convert With Truncation Scalar Double Precision Floating-Point Value to SignedInteger</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>CVTTSD2SI
— Convert With Truncation Scalar Double Precision Floating-Point Value to SignedInteger</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F 2C /r CVTTSD2SI r32, xmm1/m64</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.</td></tr>
<tr>
<td>F2 REX.W 0F 2C /r CVTTSD2SI r64, xmm1/m64</td>
<td>A</td>
<td>V/N.E.</td>
<td>SSE2</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.W0 2C /r <sup>1</sup> VCVTTSD2SI r32, xmm1/m64</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.</td></tr>
<tr>
<td>VEX.LIG.F2.0F.W1 2C /r <sup>1</sup> VCVTTSD2SI r64, xmm1/m64</td>
<td>B</td>
<td>V/N.E.<sup>2</sup></td>
<td>AVX</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W0 2C /r VCVTTSD2SI r32, xmm1/m64{sae}</td>
<td>B</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation.</td></tr>
<tr>
<td>EVEX.LLIG.F2.0F.W1 2C /r VCVTTSD2SI r64, xmm1/m64{sae}</td>
<td>B</td>
<td>V/N.E.<sup>2</sup></td>
<td>AVX512F</td>
<td>Convert one double precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation.</td></tr></table>
<blockquote>
<p>1. Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<p>2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.</p></blockquote>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>Tuple1 Fixed</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Converts a double precision floating-point value in the source operand (the second operand) to a signed double-word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general purpose register. When the source operand is an XMM register, the double precision floating-point value is contained in the low quadword of the register.</p>
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.</p>
<p>If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.</p>
<p>If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000_00000000H) is returned.</p>
<p>Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits.</p>
<p>VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
<p>Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="-v-cvttsd2si--all-versions-">(V)CVTTSD2SI (All Versions)<a class="anchor" href="#-v-cvttsd2si--all-versions-">
</a></h3>
<pre>IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
FI;
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);
</pre>
<pre>VCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);
</pre>
<pre>VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);
</pre>
<pre>VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);
</pre>
<pre>CVTTSD2SI int _mm_cvttsd_si32( __m128d a);
</pre>
<pre>CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);
</pre>
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h2>
<p>Invalid, Precision.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>VEX-encoded instructions, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions,” additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If VEX.vvvv != 1111B.</td></tr></table>
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-48</span>, “Type E3NF Class Exception Conditions.”</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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