103 lines
5.4 KiB
HTML
103 lines
5.4 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>AESENCWIDE256KL
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— Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>AESENCWIDE256KL
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— Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F3 0F 38 D8 !(11):010:bbb AESENCWIDE256KL m512, <XMM0-7></td>
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<td>A</td>
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<td>V/V</td>
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<td>AESKLE WIDE_KL</td>
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<td>Encrypt XMM0-7 using 256-bit AES key indicated by handle at m512 and store each resultant block back to its corresponding register.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operands 2—9</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (r)</td>
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<td>Implicit XMM0-7 (r, w)</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The AESENCWIDE256KL<sup>1</sup> instruction performs 14 rounds of AES to encrypt each of the eight blocks in XMM0-7 using the 256-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7 with its corresponding encrypted block if the operation succeeds (e.g., does not run into a handle violation failure).</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h4 id="aesencwide256kl">AESENCWIDE256KL<a class="anchor" href="#aesencwide256kl">
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¶
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</a></h4>
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<pre>Handle := UnalignedLoad of 512 bit (SRC); // Load is not guaranteed to be atomic.
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Illegal Handle = (
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HandleReservedBitSet (Handle) ||
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(Handle[0] AND (CPL > 0)) ||
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Handle [1] ||
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HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256
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);
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IF (Illegal Handle)
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THEN RFLAGS.ZF := 1;
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ELSE
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(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate512 (Handle[511:0], IWKey);
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IF (Authentic == 0)
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THEN RFLAGS.ZF := 1;
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ELSE
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XMM0 := AES256Encrypt (XMM0, UnwrappedKey) ;
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XMM1 := AES256Encrypt (XMM1, UnwrappedKey) ;
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XMM2 := AES256Encrypt (XMM2, UnwrappedKey) ;
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XMM3 := AES256Encrypt (XMM3, UnwrappedKey) ;
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XMM4 := AES256Encrypt (XMM4, UnwrappedKey) ;
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XMM5 := AES256Encrypt (XMM5, UnwrappedKey) ;
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XMM6 := AES256Encrypt (XMM6, UnwrappedKey) ;
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XMM7 := AES256Encrypt (XMM7, UnwrappedKey) ;
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RFLAGS.ZF := 0;
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FI;
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FI;
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RFLAGS.OF, SF, AF, PF, CF := 0;
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1. Further details on Key Locker and usage of this instruction can be found here:
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</pre>
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<h3 id="https---software-intel-com-content-www-us-en-develop-download-intel-key-locker-specification-html-">https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.<a class="anchor" href="#https---software-intel-com-content-www-us-en-develop-download-intel-key-locker-specification-html-">
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¶
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</a></h3>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>AESENCWIDE256KLunsigned char _mm_aesencwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
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</pre>
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<h2 id="exceptions--all-operating-modes-">Exceptions (All Operating Modes)<a class="anchor" href="#exceptions--all-operating-modes-">
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¶
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</a></h2>
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<p>#UD If the LOCK prefix is used.</p>
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<p>If CPUID.07H:ECX.KL[bit 23] = 0.</p>
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<p>If CR4.KL = 0.</p>
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<p>If CPUID.19H:EBX.AESKLE[bit 0] = 0.</p>
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<p>If CR0.EM = 1.</p>
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<p>If CR4.OSFXSR = 0.</p>
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<p>If CPUID.19H:EBX.WIDE_KL[bit 2] = 0.</p>
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<p>#NM If CR0.TS = 1.</p>
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<p>#PF If a page fault occurs.</p>
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<p>#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
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<p>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</p>
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<p>If the memory address is in a non-canonical form.</p>
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<p>#SS(0) If a memory operand effective address is outside the SS segment limit.</p>
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<p>If a memory address referencing the SS segment is in a non-canonical form.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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