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2025-07-08 02:23:29 -03:00
<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>BNDMOV
— Move Bounds</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>BNDMOV
— Move Bounds</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 1A /r BNDMOV bnd1, bnd2/m64</td>
<td>RM</td>
<td>N.E./V</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2/m64 to bound register bnd1.</td></tr>
<tr>
<td>66 0F 1A /r BNDMOV bnd1, bnd2/m128</td>
<td>RM</td>
<td>V/N.E.</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2/m128 to bound register bnd1.</td></tr>
<tr>
<td>66 0F 1B /r BNDMOV bnd1/m64, bnd2</td>
<td>MR</td>
<td>N.E./V</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2 to bnd1/m64.</td></tr>
<tr>
<td>66 0F 1B /r BNDMOV bnd1/m128, bnd2</td>
<td>MR</td>
<td>V/N.E.</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2 to bound register bnd1/m128.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. The memory format for loading/store bounds in 64-bit mode is shown in <a href='bndmov.html#fig-3-5'>Figure 3-5</a>.</p>
<figure id="fig-3-5">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="56.7711470999748" x="133.44" y="34.64140924983383">Upper Bound (UB)</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="55.55452844997467" x="259.13923652" y="34.70140924983383">Lower Bound (LB)</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.82699072423975pt; fill: #000" textLength="44.05975405589487" x="458.99932715" y="64.64140924983383">0 Byteoffset</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="7.848181971789671" x="132.06" y="64.34140924983382">16</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.046990724239715pt; fill: #000" textLength="4.009074231789668" x="306.0" y="64.40140924983382">8</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="110.28677907178968" x="388.31838172000005" y="114.98140924983386">BNDMOV to memory in 32-bit mode</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="56.7115293199747" x="125.82000000000001" y="118.82140924983383">Upper Bound (UB)</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.04699072423972pt; fill: #000" textLength="55.567699819974706" x="251.51923652000002" y="118.88140924983384">Lower Bound (LB)</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 8.886990724239752pt; fill: #000" textLength="44.065299895894725" x="451.37901614000003" y="148.88140924983384">0 Byteoffset</text>
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<figcaption><a href='bndmov.html#fig-3-5'>Figure 3-5</a>. Memory Layout of BNDMOV to/from Memory</figcaption></figure>
<p>This instruction does not change flags.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="bndmov-register-to-register">BNDMOV register to register<a class="anchor" href="#bndmov-register-to-register">
</a></h3>
<pre>DEST.LB := SRC.LB;
DEST.UB := SRC.UB;
</pre>
<h3 id="bndmov-from-memory">BNDMOV from memory<a class="anchor" href="#bndmov-from-memory">
</a></h3>
<pre>IF 64-bit mode THEN
DEST.LB := LOAD_QWORD(SRC);
DEST.UB := LOAD_QWORD(SRC+8);
ELSE
DEST.LB := LOAD_DWORD_ZERO_EXT(SRC);
DEST.UB := LOAD_DWORD_ZERO_EXT(SRC+4);
FI;
</pre>
<h3 id="bndmov-to-memory">BNDMOV to memory<a class="anchor" href="#bndmov-to-memory">
</a></h3>
<pre>IF 64-bit mode THEN
DEST[63:0] := SRC.LB;
DEST[127:64] := SRC.UB;
ELSE
DEST[31:0] := SRC.LB;
DEST[63:32] := SRC.UB;
FI;
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>BNDMOV void * _bnd_copy_ptr_bounds(const void *q, const void *r)
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="4">#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr>
<tr>
<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
<tr>
<td>If 67H prefix is not used and CS.D=0.</td></tr>
<tr>
<td>If 67H prefix is used and CS.D=1.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td rowspan="3">#GP(0)</td>
<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>If the destination operand points to a non-writable segment</td></tr>
<tr>
<td>If the DS, ES, FS, or GS segment register contains a NULL segment selector.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault</td>
<td>code) If a page fault occurs.</td></tr></table>
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="3">#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr>
<tr>
<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
<tr>
<td>If 16-bit addressing is used.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr></table>
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="3">#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr>
<tr>
<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
<tr>
<td>If 16-bit addressing is used.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault</td>
<td>code) If a page fault occurs.</td></tr></table>
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
</a></h2>
<p>Same exceptions as in protected mode.</p>
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="2">#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr>
<tr>
<td>If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault</td>
<td>code) If a page fault occurs.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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