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6 KiB
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165 lines
6 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>BNDCU/BNDCN
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— Check Upper Bound</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>BNDCU/BNDCN
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— Check Upper Bound</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F2 0F 1A /r BNDCU bnd, r/m32</td>
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<td>RM</td>
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<td>N.E./V</td>
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<td>MPX</td>
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<td>Generate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form).</td></tr>
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<tr>
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<td>F2 0F 1A /r BNDCU bnd, r/m64</td>
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<td>RM</td>
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<td>V/N.E.</td>
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<td>MPX</td>
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<td>Generate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB in 1's complement form).</td></tr>
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<tr>
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<td>F2 0F 1B /r BNDCN bnd, r/m32</td>
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<td>RM</td>
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<td>N.E./V</td>
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<td>MPX</td>
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<td>Generate a #BR if the address in r/m32 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form).</td></tr>
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<tr>
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<td>F2 0F 1B /r BNDCN bnd, r/m64</td>
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<td>RM</td>
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<td>V/N.E.</td>
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<td>MPX</td>
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<td>Generate a #BR if the address in r/m64 is higher than the upper bound in bnd.UB (bnb.UB not in 1's complement form).</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Compare the address in the second operand with the upper bound in bnd. The second operand can be either a register or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to 01H and signal a #BR exception.</p>
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<p>BNDCU perform 1’s complement operation on the upper bound of bnd first before proceeding with address comparison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1’s complement form.</p>
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<p>This instruction does not cause any memory access, and does not read or write any flags.</p>
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<p>Effective address computation of m32/64 has identical behavior to LEA</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="bndcu-bnd--reg">BNDCU BND, reg<a class="anchor" href="#bndcu-bnd--reg">
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¶
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</a></h3>
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<pre>IF reg > NOT(BND.UB) Then
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BNDSTATUS := 01H;
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#BR;
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FI;
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</pre>
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<h3 id="bndcu-bnd--mem">BNDCU BND, mem<a class="anchor" href="#bndcu-bnd--mem">
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¶
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</a></h3>
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<pre>TEMP := LEA(mem);
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IF TEMP > NOT(BND.UB) Then
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BNDSTATUS := 01H;
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#BR;
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FI;
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</pre>
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<h3 id="bndcn-bnd--reg">BNDCN BND, reg<a class="anchor" href="#bndcn-bnd--reg">
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¶
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</a></h3>
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<pre>IF reg > BND.UB Then
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BNDSTATUS := 01H;
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#BR;
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FI;
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</pre>
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<h3 id="bndcn-bnd--mem">BNDCN BND, mem<a class="anchor" href="#bndcn-bnd--mem">
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¶
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</a></h3>
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<pre>TEMP := LEA(mem);
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IF TEMP > BND.UB Then
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BNDSTATUS := 01H;
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#BR;
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FI;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>BNDCU .void _bnd_chk_ptr_ubounds(const void *q)
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#BR</td>
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<td>If upper bound check fails.</td></tr>
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<tr>
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<td rowspan="4">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
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<tr>
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<td>If 67H prefix is not used and CS.D=0.</td></tr>
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<tr>
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<td>If 67H prefix is used and CS.D=1.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#BR</td>
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<td>If upper bound check fails.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
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<tr>
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<td>If 16-bit addressing is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#BR</td>
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<td>If upper bound check fails.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</td></tr>
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<tr>
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<td>If 16-bit addressing is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#UD</td>
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<td>If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.</td></tr></table>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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