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241 lines
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XRSTORS
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— Restore Processor Extended States Supervisor</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XRSTORS
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— Restore Processor Extended States Supervisor</h1>
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<table>
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<tr>
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<th>Opcode / Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F C7 /3 XRSTORS mem</td>
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<td>M</td>
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<td>V/V</td>
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<td>XSS</td>
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<td>Restore state components specified by EDX:EAX from mem.</td></tr>
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<tr>
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<td>NP REX.W + 0F C7 /3 XRSTORS64 mem</td>
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<td>M</td>
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<td>V/N.E.</td>
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<td>XSS</td>
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<td>Restore state components specified by EDX:EAX from mem.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a full or partial restore of processor state components from the XSAVE area located at the memory address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XRSTORS may be executed only if CPL = 0.</p>
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<p>The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. Like FXRSTOR and FXSAVE, the memory format used for x87 state depends on a REX.W prefix; see Section 13.5.1, “x87 State” of Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.</p>
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<p>Section 13.12, “Operation of XRSTORS,” of Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a high-level outline:</p>
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<ul>
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<li>Execution of XRSTORS is similar to that of the compacted form of XRSTOR; XRSTORS cannot restore from an XSAVE area in which the extended region is in the standard format (see Section 13.4.3, “Extended Region of an XSAVE Area” of Intel<sup>® </sup>64 and IA-32 Architectures Software Developer’s Manual, Volume 1).</li>
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<li>XRSTORS differs from XRSTOR in that it can restore state components corresponding to bits set in the IA32_XSS MSR.</li>
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<li>If RFBM[<em>i</em>] = 0, XRSTORS does not update state component <em>i</em>.</li>
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<li>If RFBM[<em>i</em>] = 1 and bit <em>i </em>is clear in the XSTATE_BV field in the XSAVE header, XRSTORS initializes state component <em>i</em>.</li>
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<li>If RFBM[<em>i</em>] = 1 and XSTATE_BV[<em>i</em>] = 1, XRSTORS loads state component <em>i </em>from the XSAVE area.</li>
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<li>If XRSTORS attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.</li>
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<li>XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of XSAVEOPT or XSAVES.</li>
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<li>Immediately following an execution of XRSTORS, the processor tracks as in-use (not in initial configuration) any state component <em>i </em>for which RFBM[<em>i</em>] = 1 and XSTATE_BV[<em>i</em>] = 1; it tracks as modified any state component <em>i </em>for which RFBM[<em>i</em>] = 0.</li></ul>
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<p>Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.</p>
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<p>See Section 13.6, “Processor Tracking of XSAVE-Managed State,” of Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for discussion of the bitmaps XINUSE and XMODIFIED and of the quantity XRSTOR_INFO.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>RFBM := (XCR0 OR IA32_XSS) AND EDX:EAX;
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/* bitwise logical OR and AND */
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COMPMASK := XCOMP_BV field from XSAVE header;
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RSTORMASK := XSTATE_BV field from XSAVE header;
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FORMAT = COMPMASK AND 7FFFFFFF_FFFFFFFFH;
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RESTORE_FEATURES = FORMAT AND RFBM;
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TO_BE_RESTORED := RESTORE_FEATURES AND RSTORMASK;
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FORCE_INIT := RFBM AND NOT FORMAT;
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TO_BE_INITIALIZED = (RFBM AND NOT RSTORMASK) OR FORCE_INIT;
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IF TO_BE_RESTORED[0] = 1
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THEN
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XINUSE[0] := 1;
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load x87 state from legacy region of XSAVE area;
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ELSIF TO_BE_INITIALIZED[0] = 1
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THEN
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XINUSE[0] := 0;
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initialize x87 state;
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FI;
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IF TO_BE_RESTORED[1] = 1
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THEN
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XINUSE[1] := 1;
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load SSE state from legacy region of XSAVE area; // this step loads the XMM registers and MXCSR
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ELSIF TO_BE_INITIALIZED[1] = 1
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THEN
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set all XMM registers to 0;
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XINUSE[1] := 0;
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MXCSR := 1F80H;
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FI;
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NEXT_FEATURE_OFFSET = 576;
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// Legacy area and XSAVE header consume 576 bytes
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FOR i := 2 TO 62
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IF FORMAT[i] = 1
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THEN
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IF TO_BE_RESTORED[i] = 1
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THEN
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XINUSE[i] := 1;
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load XSAVE state component i at offset NEXT_FEATURE_OFFSET from base of XSAVE area;
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FI;
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NEXT_FEATURE_OFFSET = NEXT_FEATURE_OFFSET + n (n enumerated by CPUID(EAX=0DH,ECX=i):EAX);
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FI;
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IF TO_BE_INITIALIZED[i] = 1
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THEN
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XINUSE[i] := 0;
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initialize XSAVE state component i;
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FI;
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ENDFOR;
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XMODIFIED := NOT RFBM;
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IF in VMX non-root operation
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THEN VMXNR := 1;
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ELSE VMXNR := 0;
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FI;
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LAXA := linear address of XSAVE area;
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XRSTOR_INFO := CPL,VMXNR,LAXA,COMPMASK;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>XRSTORS void _xrstors( void * , unsigned __int64);
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</pre>
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<pre>XRSTORS64 void _xrstors64( void * , unsigned __int64);
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</pre>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="8">#GP(0)</td>
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<td>If CPL > 0.</td></tr>
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<tr>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If a memory operand is not aligned on a 64-byte boundary, regardless of segment.</td></tr>
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<tr>
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<td>If bit 63 of the XCOMP_BV field of the XSAVE header is 0.</td></tr>
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<tr>
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<td>If a bit in XCR0|IA32_XSS is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.</td></tr>
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<tr>
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<td>If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the XSTATE_BV field is 1.</td></tr>
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<tr>
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<td>If bytes 63:16 of the XSAVE header are not all zero.</td></tr>
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<tr>
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<td>If attempting to write any reserved bits of the MXCSR register with 1.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#NM</td>
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<td>If CR0.TS[bit 3] = 1.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.</td></tr>
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<tr>
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<td>If CR4.OSXSAVE[bit 18] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="7">#GP</td>
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<td>If a memory operand is not aligned on a 64-byte boundary, regardless of segment.</td></tr>
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<tr>
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<td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
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<tr>
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<td>If bit 63 of the XCOMP_BV field of the XSAVE header is 0.</td></tr>
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<tr>
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<td>If a bit in XCR0|IA32_XSS is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.</td></tr>
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<tr>
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<td>If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the XSTATE_BV field is 1.</td></tr>
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<tr>
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<td>If bytes 63:16 of the XSAVE header are not all zero.</td></tr>
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<tr>
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<td>If attempting to write any reserved bits of the MXCSR register with 1.</td></tr>
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<tr>
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<td>#NM</td>
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<td>If CR0.TS[bit 3] = 1.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.</td></tr>
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<tr>
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<td>If CR4.OSXSAVE[bit 18] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="8">#GP(0)</td>
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<td>If CPL > 0.</td></tr>
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<tr>
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<td>If a memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not aligned on a 64-byte boundary, regardless of segment.</td></tr>
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<tr>
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<td>If bit 63 of the XCOMP_BV field of the XSAVE header is 0.</td></tr>
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<tr>
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<td>If a bit in XCR0|IA32_XSS is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.</td></tr>
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<tr>
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<td>If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the XSTATE_BV field is 1.</td></tr>
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<tr>
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<td>If bytes 63:16 of the XSAVE header are not all zero.</td></tr>
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<tr>
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<td>If attempting to write any reserved bits of the MXCSR register with 1.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#NM</td>
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<td>If CR0.TS[bit 3] = 1.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.</td></tr>
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<tr>
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<td>If CR4.OSXSAVE[bit 18] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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