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5.5 KiB
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140 lines
5.5 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VRCPPH
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— Compute Reciprocals of Packed FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VRCPPH
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— Compute Reciprocals of Packed FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En bit Mode Flag
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Support Instruction En bit Mode Flag
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Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.MAP6.W0 4C /r VRCPPH xmm1{k1}{z}, xmm2/m128/m16bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Compute the approximate reciprocals of packed FP16 values in xmm2/m128/m16bcst and store the result in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.MAP6.W0 4C /r VRCPPH ymm1{k1}{z}, ymm2/m256/m16bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Compute the approximate reciprocals of packed FP16 values in ymm2/m256/m16bcst and store the result in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.MAP6.W0 4C /r VRCPPH zmm1{k1}{z}, zmm2/m512/m16bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Compute the approximate reciprocals of packed FP16 values in zmm2/m512/m16bcst and store the result in zmm1 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction performs a SIMD computation of the approximate reciprocals of 8/16/32 packed FP16 values in the source operand (the second operand) and stores the packed FP16 results in the destination operand. The maximum relative error for this approximation is less than 2<sup>−11</sup> + 2<sup>−14</sup>.</p>
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<p>For special cases, see <a href='vrcpph.html#tbl-5-28'>Table 5-28</a>.</p>
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<figure id="tbl-5-28">
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<table>
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<tr>
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<th>Input Value</th>
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<th>Result Value</th>
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<th>Comments</th></tr>
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<tr>
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<td>0 ≤ X ≤ 2<sup>-16</sup></td>
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<td>INF</td>
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<td>Very small denormal</td></tr>
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<tr>
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<td>−2<sup>-16</sup> ≤ X ≤ -0</td>
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<td>−INF</td>
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<td>Very small denormal</td></tr>
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<tr>
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<td>X > +∞</td>
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<td>+0</td>
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<td></td></tr>
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<tr>
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<td>X < −∞</td>
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<td>−0</td>
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<td></td></tr>
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<tr>
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<td><sub>X = 2</sub>-n</td>
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<td><sub>2</sub><sup>n</sup></td>
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<td></td></tr>
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<tr>
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<td>X = −2<sup>-n</sup></td>
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<td>−2<sup>n</sup></td>
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<td></td></tr></table>
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<figcaption><a href='vrcpph.html#tbl-5-28'>Table 5-28</a>. VRCPPH/VRCPSH Special Cases</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vrcpph-dest-k1---src">VRCPPH dest{k1}, src<a class="anchor" href="#vrcpph-dest-k1---src">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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FOR i := 0 to KL-1:
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IF k1[i] or *no writemask*:
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IF SRC is memory and (EVEX.b = 1):
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tsrc := src.fp16[0]
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ELSE:
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tsrc := src.fp16[i]
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DEST.fp16[i] := APPROXIMATE(1.0 / tsrc)
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ELSE IF *zeroing*:
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DEST.fp16[i] := 0
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//else DEST.fp16[i] remains unchanged
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VRCPPH __m128h _mm_mask_rcp_ph (__m128h src, __mmask8 k, __m128h a);
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</pre>
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<pre>VRCPPH __m128h _mm_maskz_rcp_ph (__mmask8 k, __m128h a);
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</pre>
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<pre>VRCPPH __m128h _mm_rcp_ph (__m128h a);
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</pre>
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<pre>VRCPPH __m256h _mm256_mask_rcp_ph (__m256h src, __mmask16 k, __m256h a);
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</pre>
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<pre>VRCPPH __m256h _mm256_maskz_rcp_ph (__mmask16 k, __m256h a);
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</pre>
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<pre>VRCPPH __m256h _mm256_rcp_ph (__m256h a);
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</pre>
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<pre>VRCPPH __m512h _mm512_mask_rcp_ph (__m512h src, __mmask32 k, __m512h a);
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</pre>
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<pre>VRCPPH __m512h _mm512_maskz_rcp_ph (__mmask32 k, __m512h a);
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</pre>
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<pre>VRCPPH __m512h _mm512_rcp_ph (__m512h a);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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