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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VFCMADDCSH/VFMADDCSH
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— Complex Multiply and Accumulate Scalar FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VFCMADDCSH/VFMADDCSH
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— Complex Multiply and Accumulate Scalar FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En Bit Mode Flag
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Support Instruction En Bit Mode Flag
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Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.F2.MAP6.W0 57 /r VFCMADDCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Complex multiply a pair of FP16 values from xmm2 and complex conjugate of xmm3/m32, add to xmm1 and store the result in xmm1 subject to writemask k1. Bits 127:32 of xmm2 are copied to xmm1[127:32].</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.MAP6.W0 57 /r VFMADDCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Complex multiply a pair of FP16 values from xmm2 and xmm3/m32, add to xmm1 and store the result in xmm1 subject to writemask k1. Bits 127:32 of xmm2 are copied to xmm1[127:32].</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Scalar</td>
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<td>ModRM:reg (r, w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction performs a complex multiply and accumulate operation. There are normal and complex conjugate forms of the operation.</p>
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<p>The masking for this operation is done on 32-bit quantities representing a pair of FP16 values.</p>
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<p>Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according to the writemask.</p>
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<p>Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR exceptions are masked. MXCSR status bits are updated to reflect exceptional conditions.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vfcmaddcsh-dest-k1---src1--src2--avx512-">VFCMADDCSH dest{k1}, src1, src2 (AVX512)<a class="anchor" href="#vfcmaddcsh-dest-k1---src1--src2--avx512-">
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¶
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</a></h4>
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<pre>IF k1[0] or *no writemask*:
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tmp[0] := dest.fp16[0] + src1.fp16[0] * src2.fp16[0]
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tmp[1] := dest.fp16[1] + src1.fp16[1] * src2.fp16[0]
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// conjugate version subtracts odd final term
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dest.fp16[0] := tmp[0] + src1.fp16[1] * src2.fp16[1]
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dest.fp16[1] := tmp[1] - src1.fp16[0] * src2.fp16[1]
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ELSE IF *zeroing*:
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dest.fp16[0] := 0
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dest.fp16[1] := 0
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DEST[127:32] := src1[127:32] // copy upper part of src1
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfmaddcsh-dest-k1---src1--src2--avx512-">VFMADDCSH dest{k1}, src1, src2 (AVX512)<a class="anchor" href="#vfmaddcsh-dest-k1---src1--src2--avx512-">
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¶
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</a></h4>
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<pre>IF k1[0] or *no writemask*:
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tmp[0] := dest.fp16[0] + src1.fp16[0] * src2.fp16[0]
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tmp[1] := dest.fp16[1] + src1.fp16[1] * src2.fp16[0]
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// non-conjugate version subtracts last even term
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dest.fp16[0] := tmp[0] - src1.fp16[1] * src2.fp16[1]
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dest.fp16[1] := tmp[1] + src1.fp16[0] * src2.fp16[1]
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ELSE IF *zeroing*:
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dest.fp16[0] := 0
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dest.fp16[1] := 0
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DEST[127:32] := src1[127:32] // copy upper part of src1
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VFCMADDCSH __m128h _mm_fcmadd_round_sch (__m128h a, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_mask_fcmadd_round_sch (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_mask3_fcmadd_round_sch (__m128h a, __m128h b, __m128h c, __mmask8 k, const int rounding);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_maskz_fcmadd_round_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_fcmadd_sch (__m128h a, __m128h b, __m128h c);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_mask_fcmadd_sch (__m128h a, __mmask8 k, __m128h b, __m128h c);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_mask3_fcmadd_sch (__m128h a, __m128h b, __m128h c, __mmask8 k);
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</pre>
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<pre>VFCMADDCSH __m128h _mm_maskz_fcmadd_sch (__mmask8 k, __m128h a, __m128h b, __m128h c);
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</pre>
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<pre>VFMADDCSH __m128h _mm_fmadd_round_sch (__m128h a, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFMADDCSH __m128h _mm_mask_fmadd_round_sch (__m128h a, __mmask8 k, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFMADDCSH __m128h _mm_mask3_fmadd_round_sch (__m128h a, __m128h b, __m128h c, __mmask8 k, const int rounding);
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</pre>
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<pre>VFMADDCSH __m128h _mm_maskz_fmadd_round_sch (__mmask8 k, __m128h a, __m128h b, __m128h c, const int rounding);
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</pre>
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<pre>VFMADDCSH __m128h _mm_fmadd_sch (__m128h a, __m128h b, __m128h c);
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</pre>
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<pre>VFMADDCSH __m128h _mm_mask_fmadd_sch (__m128h a, __mmask8 k, __m128h b, __m128h c);
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</pre>
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<pre>VFMADDCSH __m128h _mm_mask3_fmadd_sch (__m128h a, __m128h b, __m128h c, __mmask8 k);
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</pre>
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<pre>VFMADDCSH __m128h _mm_maskz_fmadd_sch (__mmask8 k, __m128h a, __m128h b, __m128h c);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Underflow, Overflow, Precision, Denormal.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-58</span>, “Type E10 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If (dest_reg == src1_reg) or (dest_reg == src2_reg).</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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