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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>POPF/POPFD/POPFQ
— Pop Stack Into EFLAGS Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>POPF/POPFD/POPFQ
— Pop Stack Into EFLAGS Register</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>9D</td>
<td>POPF</td>
<td>ZO</td>
<td>Valid</td>
<td>Valid</td>
<td>Pop top of stack into lower 16 bits of EFLAGS.</td></tr>
<tr>
<td>9D</td>
<td>POPFD</td>
<td>ZO</td>
<td>N.E.</td>
<td>Valid</td>
<td>Pop top of stack into EFLAGS.</td></tr>
<tr>
<td>9D</td>
<td>POPFQ</td>
<td>ZO</td>
<td>Valid</td>
<td>N.E.</td>
<td>Pop top of stack and zero-extend into RFLAGS.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>ZO</td>
<td>N/A</td>
<td>N/A</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the value in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the operation of the PUSHF/PUSHFD/PUSHFQ instructions.</p>
<p>The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD. Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to determine the size of values to pop from the stack.</p>
<p>The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See <a href='popf.popfd.popfq.html#tbl-4-16'>Table 4-16</a> and the key below for details.</p>
<p>When operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equivalent to privilege level 0), all non-reserved flags in the EFLAGS register except RF<sup>1</sup>, VIP, VIF, and VM may be modified. VIP, VIF, and VM remain unaffected.</p>
<p>When operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or equal to IOPL, all flags can be modified except the IOPL field and RF, IF, VIP, VIF, and VM; these remain unaffected. The AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur but privileged bits do not change.</p>
<p>When operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0), the POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) occurs. If the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in virtual-8086 mode with IOPL &lt; 3.</p>
<p>(The protected-mode virtual-interrupt feature — enabled by setting CR4.PVI — affects the CLI and STI instructions in the same manner as the virtual-8086 mode extensions. POPF, however, is not affected by CR4.PVI.)</p>
<p>In 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64 bits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.</p>
<p>See Chapter 3 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the EFLAGS registers.</p>
<blockquote>
<p>1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.</p></blockquote>
<figure id="tbl-4-16">
<table>
<tr>
<th rowspan="3">Mode</th>
<th rowspan="3">Operand Size</th>
<th rowspan="3">CPL</th>
<th rowspan="3">IOPL</th>
<th colspan="17">Flags</th>
<th rowspan="3">Notes</th></tr>
<tr>
<th>21</th>
<th>20</th>
<th>19</th>
<th>18</th>
<th>17</th>
<th>16</th>
<th>14</th>
<th>13:12</th>
<th>11</th>
<th>10</th>
<th>9</th>
<th>8</th>
<th>7</th>
<th>6</th>
<th>4</th>
<th>2</th>
<th>0</th></tr>
<tr>
<th>ID</th>
<th>VIP</th>
<th>VIF</th>
<th>AC</th>
<th>VM</th>
<th>RF</th>
<th>NT</th>
<th>IOPL</th>
<th>OF</th>
<th>DF</th>
<th>IF</th>
<th>TF</th>
<th>SF</th>
<th>ZF</th>
<th>AF</th>
<th>PF</th>
<th>CF</th></tr>
<tr>
<td rowspan="2"><strong>Real-Address Mode (CR0.PE = 0)</strong></td>
<td>16</td>
<td>0</td>
<td>0-3</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32</td>
<td>0</td>
<td>0-3</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td rowspan="6"><strong>Protected, Compatibility, and 64-Bit Modes (CR0.PE = 1 EFLAGS.VM = 0)</strong></td>
<td>16</td>
<td>0</td>
<td>0-3</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>16</td>
<td>1-3</td>
<td>&lt;CPL</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>16</td>
<td>1-3</td>
<td>≥CPL</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32, 64</td>
<td>0</td>
<td>0-3</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32, 64</td>
<td>1-3</td>
<td>&lt;CPL</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32, 64</td>
<td>1-3</td>
<td>≥CPL</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td rowspan="4"><strong>Virtual-8086 (CR0.PE = 1 EFLAGS.VM = 1 CR4.VME = 0)</strong></td>
<td>16</td>
<td>3</td>
<td>0-2</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>1</td></tr>
<tr>
<td>16</td>
<td>3</td>
<td>3</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32</td>
<td>3</td>
<td>0-2</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>1</td></tr>
<tr>
<td>32</td>
<td>3</td>
<td>3</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td rowspan="4"><strong>VME (CR0.PE = 1 EFLAGS.VM = 1 CR4.VME = 1)</strong></td>
<td>16</td>
<td>3</td>
<td>0-2</td>
<td>N/X</td>
<td>N/X</td>
<td>SV/X</td>
<td>N/X</td>
<td>N/X</td>
<td>0/X</td>
<td>S/X</td>
<td>N/X</td>
<td>S/X</td>
<td>S/X</td>
<td>N/X</td>
<td>S/X</td>
<td>S/X</td>
<td>S/X</td>
<td>S/X</td>
<td>S/X</td>
<td>S/X</td>
<td>2,3</td></tr>
<tr>
<td>16</td>
<td>3</td>
<td>3</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr>
<tr>
<td>32</td>
<td>3</td>
<td>0-2</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>X</td>
<td>1</td></tr>
<tr>
<td>32</td>
<td>3</td>
<td>3</td>
<td>S</td>
<td>N</td>
<td>N</td>
<td>S</td>
<td>N</td>
<td>0</td>
<td>S</td>
<td>N</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td>S</td>
<td></td></tr></table>
<figcaption><a href='popf.popfd.popfq.html#tbl-4-16'>Table 4-16</a>. Effect of POPF/POPFD on the EFLAGS Register</figcaption></figure>
<blockquote>
<p>1. #GP fault - no flag update</p>
<p>2. #GP fault with no flag update if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack</p>
<p>3. #GP fault with no flag update if TF=1 in FLAGS value on stack</p></blockquote>
<table>
<tr>
<th colspan="2">Key</th></tr>
<tr>
<td><strong>S</strong></td>
<td>Updated from stack</td></tr>
<tr>
<td><strong>SV</strong></td>
<td>Updated from IF (bit 9) in FLAGS value on stack</td></tr>
<tr>
<td><strong>N</strong></td>
<td>No change in value</td></tr>
<tr>
<td><strong>X</strong></td>
<td>No EFLAGS update</td></tr>
<tr>
<td><strong>0</strong></td>
<td>Value is cleared</td></tr></table>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<pre>IF EFLAGS.VM = 0 (* Not in Virtual-8086 Mode *)
THEN IF CPL = 0 OR CR0.PE = 0
THEN
IF OperandSize = 32;
THEN
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
ELSE IF (Operandsize = 64)
RFLAGS = Pop(); (* 64-bit pop *)
(* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
ELSE (* OperandSize = 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)
(* All non-reserved flags can be modified. *)
FI;
ELSE (* CPL &gt; 0 *)
IF OperandSize = 32
THEN
IF CPL &gt; IOPL
THEN
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM, and RF can be modified;
IF, IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
ELSE
EFLAGS := Pop(); (* 32-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE IF (Operandsize = 64)
IF CPL &gt; IOPL
THEN
RFLAGS := Pop(); (* 64-bit pop *)
(* All non-reserved bits except IF, IOPL, VIP, VIF, VM, and RF can be modified;
IF, IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
ELSE
RFLAGS := Pop(); (* 64-bit pop *)
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
IOPL, VIP, VIF, VM, and all reserved bits are unaffected; RF is cleared. *)
FI;
ELSE (* OperandSize = 16 *)
EFLAGS[15:0] := Pop(); (* 16-bit pop *)
(* All non-reserved bits except IOPL can be modified; IOPL and all
reserved bits are unaffected. *)
FI;
FI;
ELSE (* In virtual-8086 mode *)
IF IOPL = 3
THEN
IF OperandSize = 32
THEN
EFLAGS := Pop();
(* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
VIP, VIF, VM, IOPL, and all reserved bits are unaffected. RF is cleared. *)
ELSE
EFLAGS[15:0] := Pop(); FI;
(* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected. *)
FI;
ELSE (* IOPL &lt; 3 *)
IF (Operandsize = 32) OR (CR4.VME = 0)
THEN #GP(0); (* Trap to virtual-8086 monitor. *)
ELSE (* Operandsize = 16 and CR4.VME = 1 *)
tempFLAGS := Pop();
IF (EFLAGS.VIP = 1 AND tempFLAGS[9] = 1) OR tempFLAGS[8] = 1
THEN #GP(0);
ELSE
EFLAGS.VIF := tempFLAGS[9];
EFLAGS[15:0] := tempFLAGS;
(* All non-reserved bits except IOPL and IF can be modified;
IOPL, IF, and all reserved bits are unaffected. *)
FI;
FI;
FI;
FI;
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>All flags may be affected; see the Operation section for details.</p>
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#SS(0)</td>
<td>If the top of stack is not within the stack segment.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If an unaligned memory reference is made while CPL = 3 and alignment checking is enabled.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#SS</td>
<td>If the top of stack is not within the stack segment.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
</a></h2>
<table>
<tr>
<td rowspan="5">#GP(0)</td>
<td>If IOPL &lt; 3 and VME is not enabled.</td></tr>
<tr>
<td>If IOPL &lt; 3 and the 32-bit operand size is used.</td></tr>
<tr>
<td>If IOPL &lt; 3, EFLAGS.VIP = 1, and bit 9 (IF) is set in the FLAGS value on the stack.</td></tr>
<tr>
<td>If IOPL &lt; 3 and bit 8 (TF) is set in the FLAGS value on the stack.</td></tr>
<tr>
<td>If an attempt is made to execute the POPF/POPFD instruction with an operand-size override prefix.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If the top of stack is not within the stack segment.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If an unaligned memory reference is made while alignment checking is enabled.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
</a></h2>
<p>Same as for protected mode exceptions.</p>
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#SS(0)</td>
<td>If the stack address is in a non-canonical form.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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