201 lines
6.6 KiB
HTML
201 lines
6.6 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>EPA
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— Add Version Array</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>EPA
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— Add Version Array</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 0AH ENCLS[EPA]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>SGX1</td>
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<td>This leaf function adds a Version Array to the EPC.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td>EAX</td>
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<td>RBX</td>
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<td>RCX</td></tr>
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<tr>
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<td>IR</td>
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<td>EPA (In)</td>
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<td>PT_VA (In, Constant)</td>
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<td>Effective address of the EPC page (In)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This leaf function creates an empty version array in the EPC page whose logical address is given by DS:RCX, and sets up EPCM attributes for that page. At the time of execution of this instruction, the register RBX must be set to PT_VA.</p>
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<p>The table below provides additional information on the memory parameter of EPA leaf function.</p>
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<h2 id="epa-memory-parameter-semantics">EPA Memory Parameter Semantics<a class="anchor" href="#epa-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>EPCPAGE</td></tr>
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<tr>
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<td>Write access permitted by Enclave</td></tr></table>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-37">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th></th>
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<th>On Conflict </th>
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<th></th></tr>
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<tr>
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<td>EPA EPA
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VA [DS:RCX]
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Exclusive #GP EPA
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VA [DS:RCX]
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</td>
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<td>VA [DS:RCX]</td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-37</span>. Base Concurrency Restrictions of EPA</figcaption></figure>
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<figure id="tbl-38-38">
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<table>
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<tr>
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<td rowspan="3"><strong>Leaf Access On Conflict
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Access On Conflict
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</strong>EPA
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VA [DS:RCX]
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Concurrent <strong>Access On Conflict
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Access On Conflict
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</strong>EPA
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VA [DS:RCX]
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</td>
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<td rowspan="3"><strong>Parameter</strong></td>
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<td colspan="6"><strong>Additional Concurrency Restrictions</strong></td></tr>
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<tr>
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<td colspan="2"><strong>vs. EACCEPT, EACCEPTCOPY, vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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EMODPE, EMODPR, EMODT</strong></td>
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<td colspan="2"><strong>vs. EADD, EEXTEND, EINIT vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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</strong></td>
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<td colspan="2"><strong>vs. ETRACK, ETRACKC</strong></td></tr>
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<tr>
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<td><strong>Access On Conflict
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Access On Conflict
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Access Access On Conflict
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Access On Conflict
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</strong></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td></tr>
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<tr>
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<td>EPA</td>
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<td>VA [DS:RCX]</td>
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<td></td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-38</span>. Additional Concurrency Restrictions of EPA</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>IF (RBX ≠ PT_VA or DS:RCX is not 4KByte Aligned)
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THEN #GP(0); FI;
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IF (DS:RCX does not resolve within an EPC)
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THEN #PF(DS:RCX); FI;
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(* Check concurrency with other Intel SGX instructions *)
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IF (Other Intel SGX instructions accessing the page)
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THEN
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IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)
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THEN
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VMCS.Exit_reason := SGX_CONFLICT;
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VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_EXCEPTION;
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VMCS.Exit_qualification.error := 0;
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VMCS.Guest-physical_address := << translation of DS:RCX produced by paging >>;
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VMCS.Guest-linear_address := DS:RCX;
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Deliver VMEXIT;
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ELSE
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#GP(0);
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FI;
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FI;
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(* Check EPC page must be empty *)
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IF (EPCM(DS:RCX). VALID ≠ 0)
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THEN #PF(DS:RCX); FI;
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(* Clears EPC page *)
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DS:RCX[32767:0] := 0;
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EPCM(DS:RCX).PT := PT_VA;
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EPCM(DS:RCX).ENCLAVEADDRESS := 0;
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EPCM(DS:RCX).BLOCKED := 0;
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EPCM(DS:RCX).PENDING := 0;
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EPCM(DS:RCX).MODIFIED := 0;
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EPCM(DS:RCX).PR := 0;
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EPCM(DS:RCX).RWX := 0;
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EPCM(DS:RCX).VALID := 1;
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</pre>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>None</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If a memory operand effective address is outside the DS segment limit.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If another Intel SGX instruction is accessing the EPC page.</td></tr>
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<tr>
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<td>If RBX is not set to PT_VA.</td></tr>
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<tr>
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<td rowspan="3">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If a memory operand is not an EPC page.</td></tr>
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<tr>
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<td>If the EPC page is valid.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="4">#GP(0)</td>
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<td>If a memory operand is non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If another Intel SGX instruction is accessing the EPC page.</td></tr>
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<tr>
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<td>If RBX is not set to PT_VA.</td></tr>
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<tr>
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<td rowspan="3">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If a memory operand is not an EPC page.</td></tr>
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<tr>
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<td>If the EPC page is valid.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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