93 lines
3.4 KiB
HTML
93 lines
3.4 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XABORT
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— Transactional Abort</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XABORT
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— Transactional Abort</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>C6 F8 ib XABORT imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>RTM</td>
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<td>Causes an RTM abort if in RTM execution.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand2</th>
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<th>Operand3</th>
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<th>Operand4</th></tr>
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<tr>
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<td>A</td>
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<td>imm8</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="xabort">XABORT<a class="anchor" href="#xabort">
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¶
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</a></h3>
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<pre>IF RTM_ACTIVE = 0
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THEN
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Treat as NOP;
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ELSE
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GOTO RTM_ABORT_PROCESSING;
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FI;
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(* For any RTM abort condition encountered during RTM execution *)
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RTM_ABORT_PROCESSING:
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Restore architectural register state;
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Discard memory updates performed in transaction;
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Update EAX with status and XABORT argument;
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RTM_NEST_COUNT:= 0;
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RTM_ACTIVE:= 0;
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SUSLDTRK_ACTIVE := 0;
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IF 64-bit Mode
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THEN
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RIP:= fallbackRIP;
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ELSE
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EIP := fallbackEIP;
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FI;
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END
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>XABORT void _xabort( unsigned int);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.</td></tr>
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<tr>
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<td>If LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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