97 lines
4.6 KiB
HTML
97 lines
4.6 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VP4DPWSSDS
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— Dot Product of Signed Words With Dword Accumulation and Saturation(4-Iterations)</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VP4DPWSSDS
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— Dot Product of Signed Words With Dword Accumulation and Saturation(4-Iterations)</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.512.F2.0F38.W0 53 /r VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512_4VNNIW</td>
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<td>Multiply signed words from source register block indicated by zmm2 by signed words from m128 and accumulate the resulting dword results with signed saturation in zmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>A Tuple1_4X ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A</td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction computes 4 sequential register source-block dot-products of two signed word operands with doubleword accumulation and signed saturation. The memory operand is sequentially selected in each of the four steps.</p>
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<p>In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.</p>
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<p>This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest 16-bits of the mask is set to 1 or if a “no masking” encoding is used.</p>
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<p>The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation portion of this instruction.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>src_reg_id is the 5 bit index of the vector register specified in the instruction as the src1 register.
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</pre>
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<h4 id="vp4dpwssds-dest--src1--src2">VP4DPWSSDS dest, src1, src2<a class="anchor" href="#vp4dpwssds-dest--src1--src2">
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¶
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</a></h4>
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<pre>(KL,VL) = (16,512)
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N := 4
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ORIGDEST := DEST
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src_base := src_reg_id & ~ (N-1) // for src1 operand
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FOR i := 0 to KL-1:
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IF k1[i] or *no writemask*:
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FOR m := 0 to N-1:
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t := SRC2.dword[m]
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p1dword := reg[src_base+m].word[2*i] * t.word[0]
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p2dword := reg[src_base+m].word[2*i+1] * t.word[1]
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DEST.dword[i] := SIGNED_DWORD_SATURATE(DEST.dword[i] + p1dword + p2dword)
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ELSE IF *zeroing*:
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DEST.dword[i] := 0
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ELSE
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DEST.dword[i] := ORIGDEST.dword[i]
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DEST[MAX_VL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VP4DPWSSDS __m512i _mm512_4dpwssds_epi32(__m512i, __m512ix4, __m128i *);
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</pre>
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<pre>VP4DPWSSDS __m512i _mm512_mask_4dpwssds_epi32(__m512i, __mmask16, __m512ix4, __m128i *);
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</pre>
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<pre>VP4DPWSSDS __m512i _mm512_maskz_4dpwssds_epi32(__mmask16, __m512i, __m512ix4, __m128i *);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See Type E4; additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If the EVEX broadcast bit is set to 1.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the MODRM.mod = 0b11.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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