165 lines
7.9 KiB
HTML
165 lines
7.9 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VFPCLASSPD
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— Tests Types of Packed Float64 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VFPCLASSPD
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— Tests Types of Packed Float64 Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>The FPCLASSPD instruction checks the packed double precision floating-point values for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corresponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are cleared.</p>
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<p>The classification categories specified by imm8 are shown in <a href='vfpclasspd.html#fig-5-13'>Figure 5-13</a>. The classification test for each category is listed in <span class="not-imported">Table 5-14</span>.</p>
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<figure id="fig-5-13">
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<table>
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<tr>
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<td></td>
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<td>76543210</td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td></tr>
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<tr>
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<td></td>
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<td><sup>SNaN</sup></td>
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<td>Neg. Finite</td>
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<td>Denormal</td>
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<td><sup>Neg. INF</sup></td>
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<td>+INF</td>
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<td>Neg. 0</td>
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<td>+0</td>
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<td>QNaN</td></tr></table>
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<figcaption><a href='vfpclasspd.html#fig-5-13'>Figure 5-13</a>. Imm8 Byte Specifier of Special Case Floating-Point Values for VFPCLASSPD/SD/PS/SS</figcaption></figure>
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<figcaption><span class="not-imported">Table 5-14</span>. Classifier Operations for VFPCLASSPD/SD/PS/SS</figcaption>
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<p><strong>Bits Imm8[0] Imm8[1] Imm8[2] Imm8[3] Imm8[4] Imm8[5] Imm8[6] Imm8[7]</strong></p>
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<p>Category QNAN PosZero NegZero PosINF NegINF Denormal Negative SNAN</p>
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<p>Classifier Checks for Checks for Checks for Checks for Checks for Checks for Checks for Checks for QNaN +0 0 +INF INF Denormal Negative finite SNaN</p>
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<p>The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>CheckFPClassDP (tsrc[63:0], imm8[7:0]){
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//* Start checking the source operand for special type *//
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NegNum :=tsrc[63];
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IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;
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IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;
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IF (ExpAllZeros AND MXCSR.DAZ) Then
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MantAllZeros := 1;
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ELSIF (tsrc[51:0]=0h) Then
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MantAllZeros := 1;
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FI;
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ZeroNumber := ExpAllZeros AND MantAllZeros
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SignalingBit := tsrc[51];
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sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN
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qNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN
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Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0
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Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0
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PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf
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NInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -Inf
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Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denorm
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FinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
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bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
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( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
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( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
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( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );
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Return bResult;
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} //* end of CheckFPClassDP() *//
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</pre>
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<h4 id="vfpclasspd--evex-encoded-versions-">VFPCLASSPD (EVEX Encoded versions)<a class="anchor" href="#vfpclasspd--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask*
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THEN
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IF (EVEX.b == 1) AND (SRC *is memory*)
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THEN
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DEST[j] := CheckFPClassDP(SRC1[63:0], imm8[7:0]);
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ELSE
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DEST[j] := CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);
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FI;
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ELSE DEST[j] := 0
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; zeroing-masking only
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FI;
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ENDFOR
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DEST[MAX_KL-1:KL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);
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</pre>
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<pre>VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)
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</pre>
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<pre>VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)
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</pre>
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<pre>VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)
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</pre>
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<pre>VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)
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</pre>
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<pre>VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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