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7.9 KiB
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193 lines
7.9 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PEXTRB/PEXTRD/PEXTRQ
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— Extract Byte/Dword/Qword</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PEXTRB/PEXTRD/PEXTRQ
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— Extract Byte/Dword/Qword</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/ En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 3A 14 /r ib PEXTRB reg/m8, xmm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r32 or r64 are zeroed.</td></tr>
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<tr>
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<td>66 0F 3A 16 /r ib PEXTRD r/m32, xmm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r/m32.</td></tr>
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<tr>
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<td>66 REX.W 0F 3A 16 /r ib PEXTRQ r/m64, xmm2, imm8</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>SSE4_1</td>
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<td>Extract a qword integer value from xmm2 at the source qword offset specified by imm8 into r/m64.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.W0 14 /r ib VPEXTRB reg/m8, xmm2, imm8</td>
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<td>A</td>
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<td>V<sup>1</sup>/V</td>
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<td>AVX</td>
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<td>Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r64/r32 is filled with zeros.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.W0 16 /r ib VPEXTRD r32/m32, xmm2, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r32/m32.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.W1 16 /r ib VPEXTRQ r64/m64, xmm2, imm8</td>
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<td>A</td>
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<td>V/I<sup>2</sup></td>
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<td>AVX</td>
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<td>Extract a qword integer value from xmm2 at the source dword offset specified by imm8 into r64/m64.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.WIG 14 /r ib VPEXTRB reg/m8, xmm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r64/r32 is filled with zeros.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W0 16 /r ib VPEXTRD r32/m32, xmm2, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r32/m32.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W1 16 /r ib VPEXTRQ r64/m64, xmm2, imm8</td>
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<td>B</td>
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<td>V/N.E.<sup>2</sup></td>
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<td>AVX512DQ</td>
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<td>Extract a qword integer value from xmm2 at the source dword offset specified by imm8 into r64/m64.</td></tr></table>
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<blockquote>
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<p>1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).</p>
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<p>2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Extract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword offset determined from imm8[3:0]. The destination can be a register or byte/dword/qword memory location. If the destination is a register, the upper bits of the register are zero extended.</p>
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<p>In legacy non-VEX encoded version and if the destination operand is a register, the default operand size in 64-bit mode for PEXTRB/PEXTRD is 64 bits, the bits above the least significant byte/dword data are filled with zeros. PEXTRQ is not encodable in non-64-bit modes and requires REX.W in 64-bit mode.</p>
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<p>Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L”L must be 0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit mode for VPEXTRB/VPEXTRD is 64 bits, the bits above the least significant byte/word/dword data are filled with zeros.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>CASE of
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PEXTRB: SEL := COUNT[3:0];
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TEMP := (Src >> SEL*8) AND FFH;
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IF (DEST = Mem8)
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THEN
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Mem8 := TEMP[7:0];
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ELSE IF (64-Bit Mode and 64-bit register selected)
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THEN
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R64[7:0] := TEMP[7:0];
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r64[63:8] := ZERO_FILL; };
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ELSE
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R32[7:0] := TEMP[7:0];
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r32[31:8] := ZERO_FILL; };
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FI;
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PEXTRD:SEL := COUNT[1:0];
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TEMP := (Src >> SEL*32) AND FFFF_FFFFH;
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DEST := TEMP;
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PEXTRQ: SEL := COUNT[0];
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TEMP := (Src >> SEL*64);
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DEST := TEMP;
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EASC:
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</pre>
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<h3 id="vpextrtd-vpextrq">VPEXTRTD/VPEXTRQ<a class="anchor" href="#vpextrtd-vpextrq">
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¶
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</a></h3>
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<pre>IF (64-Bit Mode and 64-bit dest operand)
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THEN
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Src_Offset := imm8[0]
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r64/m64 := (Src >> Src_Offset * 64)
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ELSE
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Src_Offset := imm8[1:0]
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r32/m32 := ((Src >> Src_Offset *32) AND 0FFFFFFFFh);
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FI
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</pre>
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<h3 id="vpextrb---dest=m8-">VPEXTRB ( dest=m8)<a class="anchor" href="#vpextrb---dest=m8-">
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¶
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</a></h3>
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<pre>SRC_Offset := imm8[3:0]
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Mem8 := (Src >> Src_Offset*8)
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</pre>
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<h3 id="vpextrb---dest=reg-">VPEXTRB ( dest=reg)<a class="anchor" href="#vpextrb---dest=reg-">
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¶
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</a></h3>
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<pre>IF (64-Bit Mode )
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THEN
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SRC_Offset := imm8[3:0]
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DEST[7:0] := ((Src >> Src_Offset*8) AND 0FFh)
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DEST[63:8] := ZERO_FILL;
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ELSE
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SRC_Offset := imm8[3:0];
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DEST[7:0] := ((Src >> Src_Offset*8) AND 0FFh);
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DEST[31:8] := ZERO_FILL;
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FI
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>PEXTRB int _mm_extract_epi8 (__m128i src, const int ndx);
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</pre>
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<pre>PEXTRD int _mm_extract_epi32 (__m128i src, const int ndx);
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</pre>
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<pre>PEXTRQ __int64 _mm_extract_epi64 (__m128i src, const int ndx);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-57</span>, “Type E9NF Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If VEX.L = 1 or EVEX.L’L > 0.</td></tr>
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<tr>
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<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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