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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PCMPGTB/PCMPGTW/PCMPGTD
— Compare Packed Signed Integers for Greater Than</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PCMPGTB/PCMPGTW/PCMPGTD
— Compare Packed Signed Integers for Greater Than</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>NP 0F 64 /r<sup>1</sup> PCMPGTB mm, mm/m64</td>
<td>A</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed byte integers in mm and mm/m64 for greater than.</td></tr>
<tr>
<td>66 0F 64 /r PCMPGTB xmm1, xmm2/m128</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed byte integers in xmm1 and xmm2/m128 for greater than.</td></tr>
<tr>
<td>NP 0F 65 /r<sup>1</sup> PCMPGTW mm, mm/m64</td>
<td>A</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed word integers in mm and mm/m64 for greater than.</td></tr>
<tr>
<td>66 0F 65 /r PCMPGTW xmm1, xmm2/m128</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed word integers in xmm1 and xmm2/m128 for greater than.</td></tr>
<tr>
<td>NP 0F 66 /r<sup>1</sup> PCMPGTD mm, mm/m64</td>
<td>A</td>
<td>V/V</td>
<td>MMX</td>
<td>Compare packed signed doubleword integers in mm and mm/m64 for greater than.</td></tr>
<tr>
<td>66 0F 66 /r PCMPGTD xmm1, xmm2/m128</td>
<td>A</td>
<td>V/V</td>
<td>SSE2</td>
<td>Compare packed signed doubleword integers in xmm1 and xmm2/m128 for greater than.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 64 /r VPCMPGTB xmm1, xmm2, xmm3/m128</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 65 /r VPCMPGTW xmm1, xmm2, xmm3/m128</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed word integers in xmm2 and xmm3/m128 for greater than.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 66 /r VPCMPGTD xmm1, xmm2, xmm3/m128</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Compare packed signed doubleword integers in xmm2 and xmm3/m128 for greater than.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 64 /r VPCMPGTB ymm1, ymm2, ymm3/m256</td>
<td>B</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 65 /r VPCMPGTW ymm1, ymm2, ymm3/m256</td>
<td>B</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed word integers in ymm2 and ymm3/m256 for greater than.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 66 /r VPCMPGTD ymm1, ymm2, ymm3/m256</td>
<td>B</td>
<td>V/V</td>
<td>AVX2</td>
<td>Compare packed signed doubleword integers in ymm2 and ymm3/m256 for greater than.</td></tr>
<tr>
<td>EVEX.128.66.0F.W0 66 /r VPCMPGTD k1 {k2}, xmm2, xmm3/m128/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Compare Greater between int32 vector xmm2 and int32 vector xmm3/m128/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.256.66.0F.W0 66 /r VPCMPGTD k1 {k2}, ymm2, ymm3/m256/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Compare Greater between int32 vector ymm2 and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.512.66.0F.W0 66 /r VPCMPGTD k1 {k2}, zmm2, zmm3/m512/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Compare Greater between int32 elements in zmm2 and zmm3/m512/m32bcst, and set destination k1 according to the comparison results under writemask. k2.</td></tr>
<tr>
<td>EVEX.128.66.0F.WIG 64 /r VPCMPGTB k1 {k2}, xmm2, xmm3/m128</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.256.66.0F.WIG 64 /r VPCMPGTB k1 {k2}, ymm2, ymm3/m256</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.512.66.0F.WIG 64 /r VPCMPGTB k1 {k2}, zmm2, zmm3/m512</td>
<td>D</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Compare packed signed byte integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.128.66.0F.WIG 65 /r VPCMPGTW k1 {k2}, xmm2, xmm3/m128</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed word integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.256.66.0F.WIG 65 /r VPCMPGTW k1 {k2}, ymm2, ymm3/m256</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Compare packed signed word integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
<tr>
<td>EVEX.512.66.0F.WIG 65 /r VPCMPGTW k1 {k2}, zmm2, zmm3/m512</td>
<td>D</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Compare packed signed word integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
<blockquote>
<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>C</td>
<td>Full</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>D</td>
<td>Full Mem</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Performs an SIMD signed compare for the greater value of the packed byte, word, or doubleword integers in the destination operand (first operand) and the source operand (second operand). If a data element in the destination operand is greater than the corresponding date element in the source operand, the corresponding data element in the destination operand is set to all 1s; otherwise, it is set to all 0s.</p>
<p>The PCMPGTB instruction compares the corresponding signed byte integers in the destination and source operands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source operands; and the PCMPGTD instruction compares the corresponding signed doubleword integers in the destination and source operands.</p>
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.</p>
<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<p>EVEX encoded VPCMPGTD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
<p>EVEX encoded VPCMPGTB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="pcmpgtb--with-64-bit-operands-">PCMPGTB (With 64-bit Operands)<a class="anchor" href="#pcmpgtb--with-64-bit-operands-">
</a></h3>
<pre>IF DEST[7:0] &gt; SRC[7:0]
THEN DEST[7:0) := FFH;
ELSE DEST[7:0] := 0; FI;
(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
IF DEST[63:56] &gt; SRC[63:56]
THEN DEST[63:56] := FFH;
ELSE DEST[63:56] := 0; FI;
</pre>
<h3 id="compare_bytes_greater--src1--src2-">COMPARE_BYTES_GREATER (SRC1, SRC2)<a class="anchor" href="#compare_bytes_greater--src1--src2-">
</a></h3>
<pre> IF SRC1[7:0] &gt; SRC2[7:0]
THEN DEST[7:0] := FFH;
ELSE DEST[7:0] := 0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
IF SRC1[127:120] &gt; SRC2[127:120]
THEN DEST[127:120] := FFH;
ELSE DEST[127:120] := 0; FI;
</pre>
<h3 id="compare_words_greater--src1--src2-">COMPARE_WORDS_GREATER (SRC1, SRC2)<a class="anchor" href="#compare_words_greater--src1--src2-">
</a></h3>
<pre> IF SRC1[15:0] &gt; SRC2[15:0]
THEN DEST[15:0] := FFFFH;
ELSE DEST[15:0] := 0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
IF SRC1[127:112] &gt; SRC2[127:112]
THEN DEST[127:112] := FFFFH;
ELSE DEST[127:112] := 0; FI;
</pre>
<h3 id="compare_dwords_greater--src1--src2-">COMPARE_DWORDS_GREATER (SRC1, SRC2)<a class="anchor" href="#compare_dwords_greater--src1--src2-">
</a></h3>
<pre> IF SRC1[31:0] &gt; SRC2[31:0]
THEN DEST[31:0] := FFFFFFFFH;
ELSE DEST[31:0] := 0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
IF SRC1[127:96] &gt; SRC2[127:96]
THEN DEST[127:96] := FFFFFFFFH;
ELSE DEST[127:96] := 0; FI;
</pre>
<h3 id="pcmpgtb--with-128-bit-operands-">PCMPGTB (With 128-bit Operands)<a class="anchor" href="#pcmpgtb--with-128-bit-operands-">
</a></h3>
<pre>DEST[127:0] := COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vpcmpgtb--vex-128-encoded-version-">VPCMPGTB (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpgtb--vex-128-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_BYTES_GREATER(SRC1,SRC2)
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vpcmpgtb--vex-256-encoded-version-">VPCMPGTB (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpgtb--vex-256-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])
DEST[MAXVL-1:256] := 0
</pre>
<h3 id="vpcmpgtb--evex-encoded-versions-">VPCMPGTB (EVEX Encoded Versions)<a class="anchor" href="#vpcmpgtb--evex-encoded-versions-">
</a></h3>
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP := SRC1[i+7:i] &gt; SRC2[i+7:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE DEST[j] := 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h3 id="pcmpgtw--with-64-bit-operands-">PCMPGTW (With 64-bit Operands)<a class="anchor" href="#pcmpgtw--with-64-bit-operands-">
</a></h3>
<pre>IF DEST[15:0] &gt; SRC[15:0]
THEN DEST[15:0] := FFFFH;
ELSE DEST[15:0] := 0; FI;
(* Continue comparison of 2nd and 3rd words in DEST and SRC *)
IF DEST[63:48] &gt; SRC[63:48]
THEN DEST[63:48] := FFFFH;
ELSE DEST[63:48] := 0; FI;
</pre>
<h3 id="pcmpgtw--with-128-bit-operands-">PCMPGTW (With 128-bit Operands)<a class="anchor" href="#pcmpgtw--with-128-bit-operands-">
</a></h3>
<pre>DEST[127:0] := COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vpcmpgtw--vex-128-encoded-version-">VPCMPGTW (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpgtw--vex-128-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_WORDS_GREATER(SRC1,SRC2)
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vpcmpgtw--vex-256-encoded-version-">VPCMPGTW (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpgtw--vex-256-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[MAXVL-1:256] := 0
</pre>
<h3 id="vpcmpgtw--evex-encoded-versions-">VPCMPGTW (EVEX Encoded Versions)<a class="anchor" href="#vpcmpgtw--evex-encoded-versions-">
</a></h3>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
CMP := SRC1[i+15:i] &gt; SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE DEST[j] := 0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h3 id="pcmpgtd--with-64-bit-operands-">PCMPGTD (With 64-bit Operands)<a class="anchor" href="#pcmpgtd--with-64-bit-operands-">
</a></h3>
<pre>IF DEST[31:0] &gt; SRC[31:0]
THEN DEST[31:0] := FFFFFFFFH;
ELSE DEST[31:0] := 0; FI;
IF DEST[63:32] &gt; SRC[63:32]
THEN DEST[63:32] := FFFFFFFFH;
ELSE DEST[63:32] := 0; FI;
</pre>
<h3 id="pcmpgtd--with-128-bit-operands-">PCMPGTD (With 128-bit Operands)<a class="anchor" href="#pcmpgtd--with-128-bit-operands-">
</a></h3>
<pre>DEST[127:0] := COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vpcmpgtd--vex-128-encoded-version-">VPCMPGTD (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpgtd--vex-128-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_DWORDS_GREATER(SRC1,SRC2)
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vpcmpgtd--vex-256-encoded-version-">VPCMPGTD (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpgtd--vex-256-encoded-version-">
</a></h3>
<pre>DEST[127:0] := COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] := COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[MAXVL-1:256] := 0
</pre>
<h3 id="vpcmpgtd--evex-encoded-versions-">VPCMPGTD (EVEX Encoded Versions)<a class="anchor" href="#vpcmpgtd--evex-encoded-versions-">
</a></h3>
<pre>(KL, VL) = (4, 128), (8, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k2[j] OR *no writemask*
THEN
/* signed comparison */
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN CMP := SRC1[i+31:i] &gt; SRC2[31:0];
ELSE CMP := SRC1[i+31:i] &gt; SRC2[i+31:i];
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE
DEST[j] := 0
; zeroing-masking only
I
;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
</a></h2>
<pre>VPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);
</pre>
<pre>VPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8_mask(__mmask64 k, __m512i a, __m512i b);
</pre>
<pre>VPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);
</pre>
<pre>VPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8_mask(__mmask32 k, __m256i a, __m256i b);
</pre>
<pre>VPCMPGTB __mmask16 _mm_cmpgt_epi8_mask(__m128i a, __m128i b);
</pre>
<pre>VPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_mask(__mmask16 k, __m128i a, __m128i b);
</pre>
<pre>VPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);
</pre>
<pre>VPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i a, __m512i b);
</pre>
<pre>VPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);
</pre>
<pre>VPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);
</pre>
<pre>VPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);
</pre>
<pre>VPCMPGTD __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);
</pre>
<pre>VPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);
</pre>
<pre>VPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_mask(__mmask32 k, __m512i a, __m512i b);
</pre>
<pre>VPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);
</pre>
<pre>VPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_mask(__mmask16 k, __m256i a, __m256i b);
</pre>
<pre>VPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);
</pre>
<pre>VPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);
</pre>
<pre>PCMPGTB __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
</pre>
<pre>PCMPGTW __m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)
</pre>
<pre>PCMPGTD __m64 _mm_cmpgt_pi32 (__m64 m1, __m64 m2)
</pre>
<pre>(V)PCMPGTB __m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)
</pre>
<pre>(V)PCMPGTW __m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)
</pre>
<pre>(V)DCMPGTD __m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b)
</pre>
<pre>VPCMPGTB __m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)
</pre>
<pre>VPCMPGTW __m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)
</pre>
<pre>VPCMPGTD __m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
<p>EVEX-encoded VPCMPGTD, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p>
<p>EVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb in <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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