180 lines
6.3 KiB
HTML
180 lines
6.3 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVSX/MOVSXD
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— Move With Sign-Extension</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVSX/MOVSXD
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— Move With Sign-Extension</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F BE /r</td>
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<td>MOVSX r16, r/m8</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move byte to word with sign-extension.</td></tr>
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<tr>
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<td>0F BE /r</td>
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<td>MOVSX r32, r/m8</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move byte to doubleword with sign-extension.</td></tr>
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<tr>
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<td>REX.W + 0F BE /r</td>
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<td>MOVSX r64, r/m8</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Move byte to quadword with sign-extension.</td></tr>
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<tr>
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<td>0F BF /r</td>
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<td>MOVSX r32, r/m16</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Move word to doubleword, with sign-extension.</td></tr>
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<tr>
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<td>REX.W + 0F BF /r</td>
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<td>MOVSX r64, r/m16</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Move word to quadword with sign-extension.</td></tr>
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<tr>
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<td>63 /r<sup>1</sup></td>
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<td>MOVSXD r16, r/m16</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Move word to word with sign-extension.</td></tr>
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<tr>
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<td>63 /r<sup>1</sup></td>
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<td>MOVSXD r32, r/m32</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Move doubleword to doubleword with sign-extension.</td></tr>
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<tr>
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<td>REX.W + 63 /r</td>
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<td>MOVSXD r64, r/m32</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Move doubleword to quadword with sign-extension.</td></tr></table>
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<blockquote>
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<p>1. The use of MOVSXD without REX.W in 64-bit mode is discouraged. Regular MOV should be used instead of using MOVSXD without REX.W.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see <span class="not-imported">Figure 7-6</span> in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1). The size of the converted value depends on the operand-size attribute.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST := SignExtend(SRC);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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