264 lines
12 KiB
HTML
264 lines
12 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVSS
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— Move or Merge Scalar Single Precision Floating-Point Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVSS
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— Move or Merge Scalar Single Precision Floating-Point Value</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F3 0F 10 /r MOVSS xmm1, xmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Merge scalar single precision floating-point value from xmm2 to xmm1 register.</td></tr>
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<tr>
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<td>F3 0F 10 /r MOVSS xmm1, m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Load scalar single precision floating-point value from m32 to xmm1 register.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.WIG 10 /r VMOVSS xmm1, xmm2, xmm3</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Merge scalar single precision floating-point value from xmm2 and xmm3 to xmm1 register</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.WIG 10 /r VMOVSS xmm1, m32</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Load scalar single precision floating-point value from m32 to xmm1 register.</td></tr>
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<tr>
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<td>F3 0F 11 /r MOVSS xmm2/m32, xmm1</td>
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<td>C</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Move scalar single precision floating-point value from xmm1 register to xmm2/m32.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.WIG 11 /r VMOVSS xmm1, xmm2, xmm3</td>
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<td>E</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move scalar single precision floating-point value from xmm2 and xmm3 to xmm1 register.</td></tr>
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<tr>
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<td>VEX.LIG.F3.0F.WIG 11 /r VMOVSS m32, xmm1</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Move scalar single precision floating-point value from xmm1 register to m32.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 10 /r VMOVSS xmm1 {k1}{z}, xmm2, xmm3</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move scalar single precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 10 /r VMOVSS xmm1 {k1}{z}, m32</td>
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<td>F</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move scalar single precision floating-point values from m32 to xmm1 under writemask k1.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 11 /r VMOVSS xmm1 {k1}{z}, xmm2, xmm3</td>
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<td>E</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move scalar single precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.0F.W0 11 /r VMOVSS m32 {k1}, xmm1</td>
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<td>G</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Move scalar single precision floating-point values from xmm1 to m32 under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>E</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>F</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>G</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Moves a scalar single precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations. This instruction can be used to move a single precision floating-point value to and from the low doubleword of an XMM register and a 32-bit memory location, or to move a single precision floating-point value between the low doublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.</p>
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<p>Legacy version: When the source and destination operands are XMM registers, bits (MAXVL-1:32) of the corresponding destination register are unmodified. When the source operand is a memory location and destination</p>
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<p>operand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAXVL:128 of the destination operand remains unchanged.</p>
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<p>VEX and EVEX encoded register-register syntax: Moves a scalar single precision floating-point value from the second source operand (the third operand) to the low doubleword element of the destination operand (the first operand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
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<p>VEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAXVL:32 of the destination operand is cleared to all 0s.</p>
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<p>EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.</p>
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<p>Note: For memory store form instruction “VMOVSS m32, xmm1”, VEX.vvvv is reserved and must be 1111b otherwise instruction will #UD. For memory store form instruction “VMOVSS mv {k1}, xmm1”, EVEX.vvvv is reserved and must be 1111b otherwise instruction will #UD.</p>
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<p>Software should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vmovss--evex-llig-f3-0f-w0-11--r-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">VMOVSS (EVEX.LLIG.F3.0F.W0 11 /r When the Source Operand is Memory and the Destination is an XMM Register)<a class="anchor" href="#vmovss--evex-llig-f3-0f-w0-11--r-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>IF k1[0] or *no writemask*
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THEN DEST[31:0] := SRC[31:0]
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI;
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FI;
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DEST[MAXVL-1:32] := 0
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</pre>
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<h3 id="vmovss--evex-llig-f3-0f-w0-10--r-when-the-source-operand-is-an-xmm-register-and-the-destination-is-memory-">VMOVSS (EVEX.LLIG.F3.0F.W0 10 /r When the Source Operand is an XMM Register and the Destination is Memory)<a class="anchor" href="#vmovss--evex-llig-f3-0f-w0-10--r-when-the-source-operand-is-an-xmm-register-and-the-destination-is-memory-">
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¶
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</a></h3>
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<pre>IF k1[0] or *no writemask*
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THEN DEST[31:0] := SRC[31:0]
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ELSE *DEST[31:0] remains unchanged* ; merging-masking
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FI;
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</pre>
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<h3 id="vmovss--evex-llig-f3-0f-w0-10-11--r-where-the-source-and-destination-are-xmm-registers-">VMOVSS (EVEX.LLIG.F3.0F.W0 10/11 /r Where the Source and Destination are XMM Registers)<a class="anchor" href="#vmovss--evex-llig-f3-0f-w0-10-11--r-where-the-source-and-destination-are-xmm-registers-">
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¶
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</a></h3>
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<pre>IF k1[0] or *no writemask*
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THEN DEST[31:0] := SRC2[31:0]
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI;
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FI;
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="movss--legacy-sse-version-when-the-source-and-destination-operands-are-both-xmm-registers-">MOVSS (Legacy SSE Version When the Source and Destination Operands are Both XMM Registers)<a class="anchor" href="#movss--legacy-sse-version-when-the-source-and-destination-operands-are-both-xmm-registers-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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DEST[MAXVL-1:32] (Unmodified)
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</pre>
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<h3 id="vmovss--vex-128-f3-0f-11--r-where-the-destination-is-an-xmm-register-">VMOVSS (VEX.128.F3.0F 11 /r Where the Destination is an XMM Register)<a class="anchor" href="#vmovss--vex-128-f3-0f-11--r-where-the-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC2[31:0]
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vmovss--vex-128-f3-0f-10--r-where-the-source-and-destination-are-xmm-registers-">VMOVSS (VEX.128.F3.0F 10 /r Where the Source and Destination are XMM Registers)<a class="anchor" href="#vmovss--vex-128-f3-0f-10--r-where-the-source-and-destination-are-xmm-registers-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC2[31:0]
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DEST[127:32] := SRC1[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vmovss--vex-128-f3-0f-10--r-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">VMOVSS (VEX.128.F3.0F 10 /r When the Source Operand is Memory and the Destination is an XMM Register)<a class="anchor" href="#vmovss--vex-128-f3-0f-10--r-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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DEST[MAXVL-1:32] := 0
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</pre>
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<h3 id="movss-vmovss--when-the-source-operand-is-an-xmm-register-and-the-destination-is-memory-">MOVSS/VMOVSS (When the Source Operand is an XMM Register and the Destination is Memory)<a class="anchor" href="#movss-vmovss--when-the-source-operand-is-an-xmm-register-and-the-destination-is-memory-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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</pre>
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<h3 id="movss--legacy-sse-version-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">MOVSS (Legacy SSE Version when the Source Operand is Memory and the Destination is an XMM Register)<a class="anchor" href="#movss--legacy-sse-version-when-the-source-operand-is-memory-and-the-destination-is-an-xmm-register-">
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¶
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</a></h3>
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<pre>DEST[31:0] := SRC[31:0]
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DEST[127:32] := 0
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);
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</pre>
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<pre>VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);
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</pre>
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<pre>VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);
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</pre>
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<pre>VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);
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</pre>
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<pre>VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);
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</pre>
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<pre>MOVSS __m128 _mm_load_ss(float * p)
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</pre>
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<pre>MOVSS void_mm_store_ss(float * p, __m128 a)
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</pre>
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<pre>MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B.</td></tr></table>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-58</span>, “Type E10 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
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</p></footer></body></html>
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