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102 lines
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVHLPS
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— Move Packed Single Precision Floating-Point Values High to Low</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVHLPS
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— Move Packed Single Precision Floating-Point Values High to Low</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 12 /r MOVHLPS xmm1, xmm2</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Move two packed single precision floating-point values from high quadword of xmm2 to low quadword of xmm1.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 12 /r VMOVHLPS xmm1, xmm2, xmm3</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Merge two packed single precision floating-point values from high quadword of xmm3 and low quadword of xmm2.</td></tr>
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<tr>
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<td>EVEX.128.0F.W0 12 /r VMOVHLPS xmm1, xmm2, xmm3</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Merge two packed single precision floating-point values from high quadword of xmm3 and low quadword of xmm2.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<sup>1</sup><a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<blockquote>
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<p>1. ModRM.MOD = 011B required.</p></blockquote>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>RVM</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r) / EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>This instruction cannot be used for memory to register moves.</p>
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<p>128-bit two-argument form:</p>
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<p>Moves two packed single precision floating-point values from the high quadword of the second XMM argument (second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of the destination operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.</p>
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<p>128-bit and EVEX three-argument form:</p>
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<p>Moves two packed single precision floating-point values from the high quadword of the third XMM argument (third operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
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<p>If VMOVHLPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="movhlps--128-bit-two-argument-form-">MOVHLPS (128-bit Two-Argument Form)<a class="anchor" href="#movhlps--128-bit-two-argument-form-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC[127:64]
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DEST[MAXVL-1:64] (Unmodified)
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</pre>
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<h3 id="vmovhlps--128-bit-three-argument-form---vex---evex-">VMOVHLPS (128-bit Three-Argument Form - VEX & EVEX)<a class="anchor" href="#vmovhlps--128-bit-three-argument-form---vex---evex-">
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¶
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</a></h3>
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<pre>DEST[63:0] := SRC2[127:64]
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DEST[127:64] := SRC1[127:64]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-24</span>, “Type 7 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.L = 1.</td></tr></table>
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<p>EVEX-encoded instruction, see Exceptions Type E7NM.128 in <span class="not-imported">Table 2-55</span>, “Type E7NM Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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