149 lines
6.4 KiB
HTML
149 lines
6.4 KiB
HTML
|
<!DOCTYPE html>
|
|||
|
|
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>FSINCOS
|
|||
|
|
— Sine and Cosine</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>FSINCOS
|
|||
|
|
— Sine and Cosine</h1>
|
|||
|
|
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<th>Opcode</th>
|
|||
|
|
<th>Instruction</th>
|
|||
|
|
<th>64-Bit Mode</th>
|
|||
|
|
<th>Compat/Leg Mode</th>
|
|||
|
|
<th>Description</th></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>D9 FB</td>
|
|||
|
|
<td>FSINCOS</td>
|
|||
|
|
<td>Valid</td>
|
|||
|
|
<td>Valid</td>
|
|||
|
|
<td>Compute the sine and cosine of ST(0); replace ST(0) with the approximate sine, and push the approximate cosine onto the register stack.</td></tr></table>
|
|||
|
|
<h2 id="description">Description<a class="anchor" href="#description">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Computes both the approximate sine and the cosine of the source operand in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the FSIN and FCOS instructions in succession.)</p>
|
|||
|
|
<p>The source operand must be given in radians and must be within the range −2<sup>63</sup> to +2<sup>63</sup>. The following table shows the results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does not occur.</p>
|
|||
|
|
<figure id="tbl-3-36">
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<th>SRC</th>
|
|||
|
|
<th colspan="2">DEST</th></tr>
|
|||
|
|
<tr>
|
|||
|
|
<th>ST(0)</th>
|
|||
|
|
<th>ST(1) Cosine</th>
|
|||
|
|
<th>ST(0) Sine</th></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>−∞</td>
|
|||
|
|
<td>*</td>
|
|||
|
|
<td>*</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>−F</td>
|
|||
|
|
<td>− 1 to + 1</td>
|
|||
|
|
<td>− 1 to + 1</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>−0</td>
|
|||
|
|
<td>+1</td>
|
|||
|
|
<td>−0</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>+0</td>
|
|||
|
|
<td>+1</td>
|
|||
|
|
<td>+0</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>+F</td>
|
|||
|
|
<td>− 1 to + 1</td>
|
|||
|
|
<td>− 1 to + 1</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>+∞</td>
|
|||
|
|
<td>*</td>
|
|||
|
|
<td>*</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>NaN</td>
|
|||
|
|
<td>NaN</td>
|
|||
|
|
<td>NaN</td></tr></table>
|
|||
|
|
<figcaption><a href='fsincos.html#tbl-3-36'>Table 3-36</a>. FSINCOS Results</figcaption></figure>
|
|||
|
|
<blockquote>
|
|||
|
|
<p>F Meansfinitefloating-pointvalue.</p>
|
|||
|
|
<p>* Indicatesfloating-pointinvalid-arithmetic-operand(#IA)exception.</p></blockquote>
|
|||
|
|
<p>If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range − 2<sup>63</sup> to +2<sup>63</sup> can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π. However, even within the range -2<sup>63</sup> to +2<sup>63</sup>, inaccurate results can occur because the finite approximation of π used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply FSINCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/8. See the sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in performing such reductions.</p>
|
|||
|
|
<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
|
|||
|
|
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<pre>IF ST(0) < 2<sup>63</sup>
|
|||
|
|
THEN
|
|||
|
|
C2 := 0;
|
|||
|
|
TEMP := fcos(ST(0)); // approximation of cosine
|
|||
|
|
ST(0) := fsin(ST(0)); // approximation of sine
|
|||
|
|
TOP := TOP − 1;
|
|||
|
|
ST(0) := TEMP;
|
|||
|
|
ELSE (* Source operand out of range *)
|
|||
|
|
C2 := 1;
|
|||
|
|
FI;
|
|||
|
|
</pre>
|
|||
|
|
<h2 id="fpu-flags-affected">FPU Flags Affected<a class="anchor" href="#fpu-flags-affected">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td rowspan="3">C1</td>
|
|||
|
|
<td>Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>Set if result was rounded up; cleared otherwise.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>C2</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>C0, C3</td>
|
|||
|
|
<td>Undefined.</td></tr></table>
|
|||
|
|
<h2 class="exceptions" id="floating-point-exceptions">Floating-Point Exceptions<a class="anchor" href="#floating-point-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td>#IS</td>
|
|||
|
|
<td>Stack underflow or overflow occurred.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#IA</td>
|
|||
|
|
<td>Source operand is an SNaN value, ∞, or unsupported format.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#D</td>
|
|||
|
|
<td>Source operand is a denormal value.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#U</td>
|
|||
|
|
<td>Result is too small for destination format.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#P</td>
|
|||
|
|
<td>Value cannot be represented exactly in destination format.</td></tr></table>
|
|||
|
|
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<table>
|
|||
|
|
<tr>
|
|||
|
|
<td>#NM</td>
|
|||
|
|
<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#MF</td>
|
|||
|
|
<td>If there is a pending x87 FPU exception.</td></tr>
|
|||
|
|
<tr>
|
|||
|
|
<td>#UD</td>
|
|||
|
|
<td>If the LOCK prefix is used.</td></tr></table>
|
|||
|
|
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p>
|
|||
|
|
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
|
|||
|
|
¶
|
|||
|
|
</a></h2>
|
|||
|
|
<p>Same exceptions as in protected mode.</p><footer><p>
|
|||
|
|
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
|||
|
|
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
|||
|
|
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
|||
|
|
</p></footer></body></html>
|