# VCVTSH2USI — Convert Low FP16 Value to Unsigned Integer

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.LLIG.F3.MAP5.W0 79 /r VCVTSH2USI r32, xmm1/m16 {er} | A | V/V1 | AVX512-FP16 | Convert the low FP16 element in xmm1/m16 to an unsigned integer and store the result in r32.
EVEX.LLIG.F3.MAP5.W1 79 /r VCVTSH2USI r64, xmm1/m16 {er} | A | V/N.E. | AVX512-FP16 | Convert the low FP16 element in xmm1/m16 to an unsigned integer and store the result in r64.

> 1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Scalar | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

### Description ¶

This instruction converts the low FP16 element in the source operand to an unsigned integer in the destination general purpose register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer indefinite value is returned.

### Operation ¶

#### VCVTSH2USI dest, src ¶

    // SET_RM() sets the rounding mode used for this instruction.
    IF *SRC is a register* and (EVEX.b = 1):
        SET_RM(EVEX.RC)
    ELSE:
        SET_RM(MXCSR.RC)
    IF 64-mode and OperandSize == 64:
        DEST.qword := Convert_fp16_to_unsigned_integer64(SRC.fp16[0])
    ELSE:
        DEST.dword := Convert_fp16_to_unsigned_integer32(SRC.fp16[0])

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCVTSH2USI unsigned int _mm_cvt_roundsh_u32 (__m128h a, int sae);

    VCVTSH2USI unsigned __int64 _mm_cvt_roundsh_u64 (__m128h a, int rounding);

    VCVTSH2USI unsigned int _mm_cvtsh_u32 (__m128h a);

    VCVTSH2USI unsigned __int64 _mm_cvtsh_u64 (__m128h a);

### SIMD Floating-Point Exceptions ¶

Invalid, Precision.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”