# VCMPSH — Compare Scalar FP16 Values

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.LLIG.F3.0F3A.W0 C2 /r /ib VCMPSH k1{k2}, xmm2, xmm3/m16 {sae}, imm8 | A | V/V | AVX512-FP16 | Compare low FP16 values in xmm3/m16 and xmm2 using bits 4:0 of imm8 as a comparison predicate subject to writemask k2, and store the result in mask register k1.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Scalar | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | imm8 (r)

### Description ¶

This instruction compares the FP16 values from the lowest element of the source operands and stores the result in the destination mask operand. The comparison predicate operand (immediate byte bits 4:0) specifies the type of comparison performed on the pair of packed FP16 values. The low destination bit is updated according to the writemask. Bits MAXKL-1:1 of the destination operand are zeroed.

### Operation ¶

    CASE (imm8 & 0x1F) OF
    0: CMP_OPERATOR := EQ_OQ;
    1: CMP_OPERATOR := LT_OS;
    2: CMP_OPERATOR := LE_OS;
    3: CMP_OPERATOR := UNORD_Q;
    4: CMP_OPERATOR := NEQ_UQ;
    5: CMP_OPERATOR := NLT_US;
    6: CMP_OPERATOR := NLE_US;
    7: CMP_OPERATOR := ORD_Q;
    8: CMP_OPERATOR := EQ_UQ;
    9: CMP_OPERATOR := NGE_US;
    10: CMP_OPERATOR := NGT_US;
    11: CMP_OPERATOR := FALSE_OQ;
    12: CMP_OPERATOR := NEQ_OQ;
    13: CMP_OPERATOR := GE_OS;
    14: CMP_OPERATOR := GT_OS;
    15: CMP_OPERATOR := TRUE_UQ;
    16: CMP_OPERATOR := EQ_OS;
    17: CMP_OPERATOR := LT_OQ;
    18: CMP_OPERATOR := LE_OQ;
    19: CMP_OPERATOR := UNORD_S;
    20: CMP_OPERATOR := NEQ_US;
    21: CMP_OPERATOR := NLT_UQ;
    22: CMP_OPERATOR := NLE_UQ;
    23: CMP_OPERATOR := ORD_S;
    24: CMP_OPERATOR := EQ_US;
    25: CMP_OPERATOR := NGE_UQ;
    26: CMP_OPERATOR := NGT_UQ;
    27: CMP_OPERATOR := FALSE_OS;
    28: CMP_OPERATOR := NEQ_OS;
    29: CMP_OPERATOR := GE_OQ;
    30: CMP_OPERATOR := GT_OQ;
    31: CMP_OPERATOR := TRUE_US;
    ESAC

#### VCMPSH (EVEX Encoded Versions) ¶

    IF k2[0] OR *no writemask*:
        DEST.bit[0] := SRC1.fp16[0] CMP_OPERATOR SRC2.fp16[0]
    ELSE
        DEST.bit[0] := 0
    DEST[MAXKL-1:1] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCMPSH __mmask8 _mm_cmp_round_sh_mask (__m128h a, __m128h b, const int imm8, const int sae);

    VCMPSH __mmask8 _mm_mask_cmp_round_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8, const int sae);

    VCMPSH __mmask8 _mm_cmp_sh_mask (__m128h a, __m128h b, const int imm8);

    VCMPSH __mmask8 _mm_mask_cmp_sh_mask (__mmask8 k1, __m128h a, __m128h b, const int imm8);

### SIMD Floating-Point Exceptions ¶

Invalid, Denormal.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”