# VMULPH — Multiply Packed FP16 Values

Instruction En bit Mode Flag Support Instruction En bit Mode Flag Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.128.NP.MAP5.W0 59 /r VMULPH xmm1{k1}{z}, xmm2, xmm3/m128/m16bcst | A | V/V | AVX512-FP16 AVX512VL | Multiply packed FP16 values from xmm3/m128/m16bcst to xmm2 and store the result in xmm1 subject to writemask k1.
EVEX.256.NP.MAP5.W0 59 /r VMULPH ymm1{k1}{z}, ymm2, ymm3/m256/m16bcst | A | V/V | AVX512-FP16 AVX512VL | Multiply packed FP16 values from ymm3/m256/m16bcst to ymm2 and store the result in ymm1 subject to writemask k1.
EVEX.512.NP.MAP5.W0 59 /r VMULPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} | A | V/V | AVX512-FP16 | Multiply packed FP16 values in zmm3/m512/m16bcst with zmm2 and store the result in zmm1 subject to writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A

### Description ¶

This instruction multiplies packed FP16 values from source operands and stores the packed FP16 result in the destination operand. The destination elements are updated according to the writemask.

### Operation ¶

#### VMULPH (EVEX encoded versions) when src2 operand is a register ¶

    VL = 128, 256 or 512
    KL := VL/16
    IF (VL = 512) AND (EVEX.b = 1):
        SET_RM(EVEX.RC)
    ELSE
        SET_RM(MXCSR.RC)
    FOR j := 0 TO KL-1:
        IF k1[j] OR *no writemask*:
            DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
        ELSE IF *zeroing*:
            DEST.fp16[j] := 0
        // else dest.fp16[j] remains unchanged
    DEST[MAXVL-1:VL] := 0

#### VMULPH (EVEX encoded versions) when src2 operand is a memory source ¶

    VL = 128, 256 or 512
    KL := VL/16
    FOR j := 0 TO KL-1:
        IF k1[j] OR *no writemask*:
            IF EVEX.b = 1:
                DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[0]
            ELSE:
                DEST.fp16[j] := SRC1.fp16[j] * SRC2.fp16[j]
        ELSE IF *zeroing*:
            DEST.fp16[j] := 0
        // else dest.fp16[j] remains unchanged
    DEST[MAXVL-1:VL] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VMULPH __m128h _mm_mask_mul_ph (__m128h src, __mmask8 k, __m128h a, __m128h b);

    VMULPH __m128h _mm_maskz_mul_ph (__mmask8 k, __m128h a, __m128h b);

    VMULPH __m128h _mm_mul_ph (__m128h a, __m128h b);

    VMULPH __m256h _mm256_mask_mul_ph (__m256h src, __mmask16 k, __m256h a, __m256h b);

    VMULPH __m256h _mm256_maskz_mul_ph (__mmask16 k, __m256h a, __m256h b);

    VMULPH __m256h _mm256_mul_ph (__m256h a, __m256h b);

    VMULPH __m512h _mm512_mask_mul_ph (__m512h src, __mmask32 k, __m512h a, __m512h b);

    VMULPH __m512h _mm512_maskz_mul_ph (__mmask32 k, __m512h a, __m512h b);

    VMULPH __m512h _mm512_mul_ph (__m512h a, __m512h b);

    VMULPH __m512h _mm512_mask_mul_round_ph (__m512h src, __mmask32 k, __m512h a, __m512h b, int rounding);

    VMULPH __m512h _mm512_maskz_mul_round_ph (__mmask32 k, __m512h a, __m512h b, int rounding);

    VMULPH __m512h _mm512_mul_round_ph (__m512h a, __m512h b, int rounding);

### SIMD Floating-Point Exceptions ¶

Invalid, Underflow, Overflow, Precision, Denormal

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”