# VCVTPD2PH — Convert Packed Double Precision FP Values to Packed FP16 Values

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.128.66.MAP5.W1 5A /r VCVTPD2PH xmm1{k1}{z}, xmm2/m128/m64bcst | A | V/V | AVX512-FP16 AVX512VL | Convert two packed double precision floating-point values in xmm2/m128/m64bcst to two packed FP16 values, and store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W1 5A /r VCVTPD2PH xmm1{k1}{z}, ymm2/m256/m64bcst | A | V/V | AVX512-FP16 AVX512VL | Convert four packed double precision floating-point values in ymm2/m256/m64bcst to four packed FP16 values, and store the result in xmm1 subject to writemask k1.
EVEX.512.66.MAP5.W1 5A /r VCVTPD2PH xmm1{k1}{z}, zmm2/m512/m64bcst {er} | A | V/V | AVX512-FP16 | Convert eight packed double precision floating-point values in zmm2/m512/m64bcst to eight packed FP16 values, and store the result in ymm1 subject to writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

### Description ¶

This instruction converts two, four, or eight packed double precision floating-point values in the source operand (second operand) to two, four, or eight packed FP16 values in the destination operand (first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasts from a 64-bit memory location. The destination operand is a XMM register conditionally updated with writemask k1. The upper bits (MAXVL-1:128/64/32) of the corresponding destination are zeroed.

EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

This instruction uses MXCSR.DAZ for handling FP64 inputs. FP16 outputs can be normal or denormal, and are not conditionally flushed to zero.

### Operation ¶

#### VCVTPD2PH DEST, SRC ¶

    VL = 128, 256 or 512
    KL := VL / 64
    IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
        SET_RM(EVEX.RC)
    ELSE:
        SET_RM(MXCSR.RC)
    FOR j := 0 TO KL-1:
        IF k1[j] OR *no writemask*:
            IF *SRC is memory* and EVEX.b = 1:
                tsrc := SRC.double[0]
            ELSE
                tsrc := SRC.double[j]
            DEST.fp16[j] := Convert_fp64_to_fp16(tsrc)
        ELSE IF *zeroing*:
            DEST.fp16[j] := 0
        // else dest.fp16[j] remains unchanged
    DEST[MAXVL-1:VL/4] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCVTPD2PH __m128h _mm512_cvt_roundpd_ph (__m512d a, int rounding);

    VCVTPD2PH __m128h _mm512_mask_cvt_roundpd_ph (__m128h src, __mmask8 k, __m512d a, int rounding);

    VCVTPD2PH __m128h _mm512_maskz_cvt_roundpd_ph (__mmask8 k, __m512d a, int rounding);

    VCVTPD2PH __m128h _mm_cvtpd_ph (__m128d a);

    VCVTPD2PH __m128h _mm_mask_cvtpd_ph (__m128h src, __mmask8 k, __m128d a);

    VCVTPD2PH __m128h _mm_maskz_cvtpd_ph (__mmask8 k, __m128d a);

    VCVTPD2PH __m128h _mm256_cvtpd_ph (__m256d a);

    VCVTPD2PH __m128h _mm256_mask_cvtpd_ph (__m128h src, __mmask8 k, __m256d a);

    VCVTPD2PH __m128h _mm256_maskz_cvtpd_ph (__mmask8 k, __m256d a);

    VCVTPD2PH __m128h _mm512_cvtpd_ph (__m512d a);

    VCVTPD2PH __m128h _mm512_mask_cvtpd_ph (__m128h src, __mmask8 k, __m512d a);

    VCVTPD2PH __m128h _mm512_maskz_cvtpd_ph (__mmask8 k, __m512d a);

### SIMD Floating-Point Exceptions ¶

Invalid, Underflow, Overflow, Precision, Denormal.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”