# VGETMANTPH — Extract FP16 Vector of Normalized Mantissas from FP16 Vector

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.128.NP.0F3A.W0 26 /r /ib VGETMANTPH xmm1{k1}{z}, xmm2/m128/m16bcst, imm8 | A | V/V | AVX512-FP16 AVX512VL | Get normalized mantissa from FP16 vector xmm2/m128/m16bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, subject to writemask k1.
EVEX.256.NP.0F3A.W0 26 /r /ib VGETMANTPH ymm1{k1}{z}, ymm2/m256/m16bcst, imm8 | A | V/V | AVX512-FP16 AVX512VL | Get normalized mantissa from FP16 vector ymm2/m256/m16bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, subject to writemask k1.
EVEX.512.NP.0F3A.W0 26 /r /ib VGETMANTPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8 | A | V/V | AVX512-FP16 | Get normalized mantissa from FP16 vector zmm2/m512/m16bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, subject to writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | ModRM:r/m (r) | imm8 (r) | N/A

### Description ¶

This instruction converts the FP16 values in the source operand (the second operand) to FP16 values with the mantissa normalization and sign control specified by the imm8 byte, see Table 5-19. The converted results are written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (SC) is specified by bits 3:2 of the immediate byte.

The destination elements are updated according to the writemask.

imm8 Bits | Definition
--- | ---
imm8[7:4] | Must be zero.
imm8[3:2] | Sign Control (SC) 0b00: Sign(SRC) 0b01: 0 0b1x: QNaN_Indefinite if sign(SRC)!=0
imm8[1:0] | Interv 0b00: Interval is [1, 2) 0b01: Interval is [1/2, 2) 0b10: Interval is [1/2, 1) 0b11: Interval is [3/4, 3/2)

Table 5-19. imm8 Controls for VGETMANTPH/VGETMANTSH

For each input FP16 value x, The conversion operation is:

GetMant(x) = ±2k|x.significand|

where:

1 ≤ |x.significand| < 2

Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is even or odd. The sign of the final result is determined by the sign control and the source sign and the leading fraction bit.

The encoded value of imm8[1:0] and sign control are shown in Table 5-19.

Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv.

The GetMant() function follows Table 5-20 when dealing with floating-point special numbers.

Input | Result | Exceptions / Comments
--- | --- | ---
NaN | QNaN(SRC) | Ignore interv. If (SRC = SNaN), then #IE.
+∞ | 1.0 | Ignore interv.
+0 | 1.0 | Ignore interv.
-0 | IF (SC[0]) THEN +1.0 ELSE -1.0 | Ignore interv.
-∞ | IF (SC[1]) THEN {QNaN_Indefinite} ELSE { IF (SC[0]) THEN +1.0 ELSE -1.0 | Ignore interv. If (SC[1]), then #IE.
negative | SC[1] ? QNaN_Indefinite : Getmant(SRC)1 | If (SC[1]), then #IE.

Table 5-20. GetMant() Special Float Values Behavior

> 1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].

### Operation ¶

    def getmant_fp16(src, sign_control, normalization_interval):
        bias := 15
        dst.sign := sign_control[0] ? 0 : src.sign
        signed_one := sign_control[0] ? +1.0 : -1.0
        dst.exp := src.exp
        dst.fraction := src.fraction
        zero := (dst.exp = 0) and (dst.fraction = 0)
        denormal := (dst.exp = 0) and (dst.fraction != 0)
        infinity := (dst.exp = 0x1F) and (dst.fraction = 0)
        nan := (dst.exp = 0x1F) and (dst.fraction != 0)
        src_signaling := src.fraction[9]
        snan := nan and (src_signaling = 0)
        positive := (src.sign = 0)
        negative := (src.sign = 1)
        if nan:
            if snan:
                MXCSR.IE := 1
            return qnan(src)
        if positive and (zero or infinity):
            return 1.0
        if negative:
            if zero:
                return signed_one
            if infinity:
                if sign_control[1]:
                    MXCSR.IE := 1
                    return QNaN_Indefinite
                return signed_one
            if sign_control[1]:
                MXCSR.IE := 1
                return QNaN_Indefinite
        if denormal:
            jbit := 0
            dst.exp := bias // set exponent to bias value
            while jbit = 0:
                jbit := dst.fraction[9]
                dst.fraction := dst.fraction << 1
                dst.exp : = dst.exp - 1
            MXCSR.DE := 1
        unbaiased_exp := dst.exp - bias
        odd_exp := unbaiased_exp[0]
        signaling_bit := dst.fraction[9]
        if normalization_interval = 0b00:
            dst.exp := bias
        else if normalization_interval = 0b01:
            dst.exp := odd_exp ? bias-1 : bias
        else if normalization_interval = 0b10:
            dst.exp := bias-1
        else if normalization_interval = 0b11:
            dst.exp := signaling_bit ? bias-1 : bias
        return dst

#### VGETMANTPH dest{k1}, src, imm8 ¶

    VL = 128, 256 or 512
    KL := VL/16
    sign_control := imm8[3:2]
    normalization_interval := imm8[1:0]
    FOR i := 0 to KL-1:
        IF k1[i] or *no writemask*:
            IF SRC is memory and (EVEX.b = 1):
                tsrc := src.fp16[0]
            ELSE:
                tsrc := src.fp16[i]
            DEST.fp16[i] := getmant_fp16(tsrc, sign_control, normalization_interval)
        ELSE IF *zeroing*:
            DEST.fp16[i] := 0
        //else DEST.fp16[i] remains unchanged
    DEST[MAXVL-1:VL] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VGETMANTPH __m128h _mm_getmant_ph (__m128h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m128h _mm_mask_getmant_ph (__m128h src, __mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m128h _mm_maskz_getmant_ph (__mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m256h _mm256_getmant_ph (__m256h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m256h _mm256_mask_getmant_ph (__m256h src, __mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m256h _mm256_maskz_getmant_ph (__mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m512h _mm512_getmant_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m512h _mm512_mask_getmant_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m512h _mm512_maskz_getmant_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);

    VGETMANTPH __m512h _mm512_getmant_round_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);

    VGETMANTPH __m512h _mm512_mask_getmant_round_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);

    VGETMANTPH __m512h _mm512_maskz_getmant_round_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);

### SIMD Floating-Point Exceptions ¶

Invalid, Denormal.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”