# KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD — Shift Right Mask Registers

Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
VEX.L0.66.0F3A.W1 30 /r KSHIFTRW k1, k2, imm8 | RRI | V/V | AVX512F | Shift right 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 30 /r KSHIFTRB k1, k2, imm8 | RRI | V/V | AVX512DQ | Shift right 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 31 /r KSHIFTRQ k1, k2, imm8 | RRI | V/V | AVX512BW | Shift right 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 31 /r KSHIFTRD k1, k2, imm8 | RRI | V/V | AVX512BW | Shift right 32 bits in k2 by immediate and write result in k1.

## Instruction Operand Encoding ¶

Op/En | Operand 1 | Operand 2 | Operand 3
--- | --- | --- | ---
RRI | ModRM:reg (w) | ModRM:r/m (r, ModRM:[7:6] must be 11b) | imm8

## Description ¶

Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

## Operation ¶

### KSHIFTRW ¶

    COUNT := imm8[7:0]
    DEST[MAX_KL-1:0] := 0
    IF COUNT <=15
        THEN DEST[15:0] := SRC1[15:0] >> COUNT;
    FI;

### KSHIFTRB ¶

    COUNT := imm8[7:0]
    DEST[MAX_KL-1:0] := 0
    IF COUNT <=7
        THEN DEST[7:0] := SRC1[7:0] >> COUNT;
    FI;

### KSHIFTRQ ¶

    COUNT := imm8[7:0]
    DEST[MAX_KL-1:0] := 0
    IF COUNT <=63
        THEN DEST[63:0] := SRC1[63:0] >> COUNT;
    FI;

### KSHIFTRD ¶

    COUNT := imm8[7:0]
    DEST[MAX_KL-1:0] := 0
    IF COUNT <=31
        THEN DEST[31:0] := SRC1[31:0] >> COUNT;
    FI;

## Intel C/C++ Compiler Intrinsic Equivalent ¶

    Compiler auto generates KSHIFTRW when needed.

## Flags Affected ¶

None.

## SIMD Floating-Point Exceptions ¶

None.

## Other Exceptions ¶

See Table 2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”