# VCVTPH2QQ — Convert Packed FP16 Values to Signed Quadword Integer Values

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.128.66.MAP5.W0 7B /r VCVTPH2QQ xmm1{k1}{z}, xmm2/m32/m16bcst | A | V/V | AVX512-FP16 AVX512VL | Convert two packed FP16 values in xmm2/m32/m16bcst to two signed quadword integers, and store the result in xmm1 subject to writemask k1.
EVEX.256.66.MAP5.W0 7B /r VCVTPH2QQ ymm1{k1}{z}, xmm2/m64/m16bcst | A | V/V | AVX512-FP16 AVX512VL | Convert four packed FP16 values in xmm2/m64/m16bcst to four signed quadword integers, and store the result in ymm1 subject to writemask k1.
EVEX.512.66.MAP5.W0 7B /r VCVTPH2QQ zmm1{k1}{z}, xmm2/m128/m16bcst {er} | A | V/V | AVX512-FP16 | Convert eight packed FP16 values in xmm2/m128/m16bcst to eight signed quadword integers, and store the result in zmm1 subject to writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Quarter | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

### Description ¶

This instruction converts packed FP16 values in the source operand to signed quadword integers in destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value is returned.

The destination elements are updated according to the writemask.

### Operation ¶

#### VCVTPH2QQ DEST, SRC ¶

    VL = 128, 256 or 512
    KL := VL / 64
    IF *SRC is a register* and (VL = 512) and (EVEX.b = 1):
        SET_RM(EVEX.RC)
    ELSE:
        SET_RM(MXCSR.RC)
    FOR j := 0 TO KL-1:
        IF k1[j] OR *no writemask*:
            IF *SRC is memory* and EVEX.b = 1:
                tsrc := SRC.fp16[0]
            ELSE
                tsrc := SRC.fp16[j]
            DEST.qword[j] := Convert_fp16_to_integer64(tsrc)
        ELSE IF *zeroing*:
            DEST.qword[j] := 0
        // else dest.qword[j] remains unchanged
    DEST[MAXVL-1:VL] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCVTPH2QQ __m512i _mm512_cvt_roundph_epi64 (__m128h a, int rounding);

    VCVTPH2QQ __m512i _mm512_mask_cvt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int rounding);

    VCVTPH2QQ __m512i _mm512_maskz_cvt_roundph_epi64 (__mmask8 k, __m128h a, int rounding);

    VCVTPH2QQ __m128i _mm_cvtph_epi64 (__m128h a);

    VCVTPH2QQ __m128i _mm_mask_cvtph_epi64 (__m128i src, __mmask8 k, __m128h a);

    VCVTPH2QQ __m128i _mm_maskz_cvtph_epi64 (__mmask8 k, __m128h a);

    VCVTPH2QQ __m256i _mm256_cvtph_epi64 (__m128h a);

    VCVTPH2QQ __m256i _mm256_mask_cvtph_epi64 (__m256i src, __mmask8 k, __m128h a);

    VCVTPH2QQ __m256i _mm256_maskz_cvtph_epi64 (__mmask8 k, __m128h a);

    VCVTPH2QQ __m512i _mm512_cvtph_epi64 (__m128h a);

    VCVTPH2QQ __m512i _mm512_mask_cvtph_epi64 (__m512i src, __mmask8 k, __m128h a);

    VCVTPH2QQ __m512i _mm512_maskz_cvtph_epi64 (__mmask8 k, __m128h a);

### SIMD Floating-Point Exceptions ¶

Invalid, Precision.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”