# SQRTPS — Square Root of Single Precision Floating-Point Values

Opcode/Instruction | Op / En | 64/32 bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
NP 0F 51 /r SQRTPS xmm1, xmm2/m128 | A | V/V | SSE | Computes Square Roots of the packed single precision floating-point values in xmm2/m128 and stores the result in xmm1.
VEX.128.0F.WIG 51 /r VSQRTPS xmm1, xmm2/m128 | A | V/V | AVX | Computes Square Roots of the packed single precision floating-point values in xmm2/m128 and stores the result in xmm1.
VEX.256.0F.WIG 51/r VSQRTPS ymm1, ymm2/m256 | A | V/V | AVX | Computes Square Roots of the packed single precision floating-point values in ymm2/m256 and stores the result in ymm1.
EVEX.128.0F.W0 51 /r VSQRTPS xmm1 {k1}{z}, xmm2/m128/m32bcst | B | V/V | AVX512VL AVX512F | Computes Square Roots of the packed single precision floating-point values in xmm2/m128/m32bcst and stores the result in xmm1 subject to writemask k1.
EVEX.256.0F.W0 51 /r VSQRTPS ymm1 {k1}{z}, ymm2/m256/m32bcst | B | V/V | AVX512VL AVX512F | Computes Square Roots of the packed single precision floating-point values in ymm2/m256/m32bcst and stores the result in ymm1 subject to writemask k1.
EVEX.512.0F.W0 51/r VSQRTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{er} | B | V/V | AVX512F | Computes Square Roots of the packed single precision floating-point values in zmm2/m512/m32bcst and stores the result in zmm1 subject to writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A
B | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

## Description ¶

Performs a SIMD computation of the square roots of the four, eight or sixteen packed single precision floating-point values in the source operand (second operand) stores the packed single precision floating-point results in the destination operand.

EVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.

VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

## Operation ¶

### VSQRTPS (EVEX Encoded Versions) ¶

    (KL, VL) = (4, 128), (8, 256), (16, 512)
    IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
        THEN
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
        ELSE
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
    FI;
    FOR j := 0 TO KL-1
        i := j * 32
        IF k1[j] OR *no writemask* THEN
                IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+31:i] := SQRT(SRC[31:0])
                    ELSE DEST[i+31:i] := SQRT(SRC[i+31:i])
                FI;
            ELSE
                IF *merging-masking* ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE ; zeroing-masking
                        DEST[i+31:i] := 0
                FI
        FI;
    ENDFOR
    DEST[MAXVL-1:VL] := 0

### VSQRTPS (VEX.256 Encoded Version) ¶

    DEST[31:0] := SQRT(SRC[31:0])
    DEST[63:32] := SQRT(SRC[63:32])
    DEST[95:64] := SQRT(SRC[95:64])
    DEST[127:96] := SQRT(SRC[127:96])
    DEST[159:128] := SQRT(SRC[159:128])
    DEST[191:160] := SQRT(SRC[191:160])
    DEST[223:192] := SQRT(SRC[223:192])
    DEST[255:224] := SQRT(SRC[255:224])

### VSQRTPS (VEX.128 Encoded Version) ¶

    DEST[31:0] := SQRT(SRC[31:0])
    DEST[63:32] := SQRT(SRC[63:32])
    DEST[95:64] := SQRT(SRC[95:64])
    DEST[127:96] := SQRT(SRC[127:96])
    DEST[MAXVL-1:128] := 0

### SQRTPS (128-bit Legacy SSE Version) ¶

    DEST[31:0] := SQRT(SRC[31:0])
    DEST[63:32] := SQRT(SRC[63:32])
    DEST[95:64] := SQRT(SRC[95:64])
    DEST[127:96] := SQRT(SRC[127:96])
    DEST[MAXVL-1:128] (Unmodified)

## Intel C/C++ Compiler Intrinsic Equivalent ¶

    VSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);

    VSQRTPS __m512 _mm512_mask_sqrt_round_ps(__m512 s, __mmask16 k, __m512 a, int r);

    VSQRTPS __m512 _mm512_maskz_sqrt_round_ps( __mmask16 k, __m512 a, int r);

    VSQRTPS __m256 _mm256_sqrt_ps (__m256 a);

    VSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);

    VSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);

    SQRTPS __m128 _mm_sqrt_ps (__m128 a);

    VSQRTPS __m128 _mm_mask_sqrt_ps(__m128 s, __mmask8 k, __m128 a, int r);

    VSQRTPS __m128 _mm_maskz_sqrt_ps( __mmask8 k, __m128 a, int r);

## SIMD Floating-Point Exceptions ¶

Invalid, Precision, Denormal.

## Other Exceptions ¶

Non-EVEX-encoded instruction, see Table 2-19, “Type 2 Class Exception Conditions,” additionally:

#UD | If VEX.vvvv != 1111B.

EVEX-encoded instruction, see Table 2-46, “Type E2 Class Exception Conditions,” additionally:

#UD | If EVEX.vvvv != 1111B.