# VADDSH — Add Scalar FP16 Values

Instruction En Bit Mode Flag Support Instruction En Bit Mode Flag Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature |  | Support |  | Description
--- | --- | --- | --- | ---
EVEX.LLIG.F3.MAP5.W0 58 /r VADDSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} | A | V/V | AVX512-FP16 | Add the low FP16 value from xmm3/m16 to xmm2, and store the result in xmm1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Scalar | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A

### Description ¶

This instruction adds the low FP16 value from the source operands and stores the FP16 result in the destination operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according to the writemask.

### Operation ¶

#### VADDSH (EVEX Encoded Versions) ¶

    IF EVEX.b = 1 and SRC2 is a register:
        SET_RM(EVEX.RC)
    ELSE
        SET_RM(MXCSR.RC)
    IF k1[0] OR *no writemask*:
        DEST.fp16[0] := SRC1.fp16[0] + SRC2.fp16[0]
    ELSEIF *zeroing*:
        DEST.fp16[0] := 0
    // else dest.fp16[0] remains unchanged
    DEST[127:16] := SRC1[127:16]
    DEST[MAXVL-1:128] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VADDSH __m128h _mm_add_round_sh (__m128h a, __m128h b, int rounding);

    VADDSH ___m128h _mm_mask_add_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);

    VADDSH ___m128h _mm_maskz_add_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);

    VADDSH ___m128h _mm_add_sh (__m128h a, __m128h b);

    VADDSH ___m128h _mm_mask_add_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

    VADDSH ___m128h _mm_maskz_add_sh (__mmask8 k, __m128h a, __m128h b);

### SIMD Floating-Point Exceptions ¶

Invalid, Underflow, Overflow, Precision, Denormal.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”