# VRANGEPS — Range Restriction Calculation for Packed Pairs of Float32 Values

Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
EVEX.128.66.0F3A.W0 50 /r ib VRANGEPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8 | A | V/V | AVX512VL AVX512DQ | Calculate four RANGE operation output value from 4 pairs of single-precision floating-point values in xmm2 and xmm3/m128/m32bcst, store the results to xmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.
EVEX.256.66.0F3A.W0 50 /r ib VRANGEPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 | A | V/V | AVX512VL AVX512DQ | Calculate eight RANGE operation output value from 8 pairs of single-precision floating-point values in ymm2 and ymm3/m256/m32bcst, store the results to ymm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.
EVEX.512.66.0F3A.W0 50 /r ib VRANGEPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{sae}, imm8 | A | V/V | AVX512DQ | Calculate 16 RANGE operation output value from 16 pairs of single-precision floating-point values in zmm2 and zmm3/m512/m32bcst, store the results to zmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.

## Instruction Operand Encoding ¶

Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | imm8

### Description ¶

This instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision floating-point values in the first source operand (the second operand) and the second source operand (the third operand). The range outputs are written to the destination operand (the first operand) under the writemask k1.

Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a two-bit control field within imm8[3:0]:

- Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min absolute value of the input value pair. Each comparison of two input values produces an intermediate result that combines with the sign selection control (imm8[3:2]) to determine the final range operation output.
- Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input value, from the comparison result, set or clear.

The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.

When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details with one of more input value is NAN is listed in Table 5-23. If the comparison raises an IE, the sign select control (imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-23.

When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare operation is slightly different from the conceptually similar floating-point MIN/MAX operation that are found in the instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magnitude-0, opposite-signed input cases are listed in Table 5-24.

Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS comparison operation with result listed in Table 5-25.

### Operation ¶

    RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
    {
        // Check if SNAN and report IE, see also Table 5-23
        IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
        IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);
        Src1.exp := SRC1[30:23];
        Src1.fraction := SRC1[22:0];
        IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
            IF DAZ THEN Src1.fraction := 0;
            ELSE IF (SRC2 <> QNAN) Set DE; FI;
        FI;
        Src2.exp := SRC2[30:23];
        Src2.fraction := SRC2[22:0];
        IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
            IF DAZ THEN Src2.fraction := 0;
            ELSE IF (SRC1 <> QNAN) Set DE; FI;
        FI;
        IF (SRC2 = QNAN) THEN{TMP[31:0] := SRC1[31:0]}
        ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] := SRC2[31:0]}
        ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] := from Table 5-24
        ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] := from Table 5-25
        ELSE
            Case(CmpOpCtl[1:0])
            00: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
            01: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
            10: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
            11: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
            ESAC;
        FI;
        Case(SignSelCtl[1:0])
        00: dest := (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
        01: dest := TMP[31:0];// Preserve sign of compare result
        10: dest := (0 << 31) OR (TMP[30:0]);// Zero out sign bit
        11: dest := (1 << 31) OR (TMP[30:0]);// Set the sign bit
        ESAC;
        RETURN dest[31:0];
    }
    CmpOpCtl[1:0]= imm8[1:0];
    SignSelCtl[1:0]=imm8[3:2];

#### VRANGEPS ¶

    (KL, VL) = (4, 128), (8, 256), (16, 512)
    FOR j := 0 TO KL-1
        i := j * 32
        IF k1[j] OR *no writemask* THEN
                IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] := RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
                    ELSE DEST[i+31:i] := RangeSP (SRC1[i+31:i], SRC2[i+31:i], CmpOpCtl[1:0], SignSelCtl[1:0]);
                FI;
        ELSE
            IF *merging-masking* ; merging-masking
                THEN *DEST[i+31:i] remains unchanged*
                ELSE ; zeroing-masking
                    DEST[i+31:i] = 0
            FI;
        FI;
    ENDFOR;
    DEST[MAXVL-1:VL] := 0
    The following example describes a common usage of this instruction for checking that the input operand is
    bounded between ±150.
    VRANGEPS zmm_dst, zmm_src, zmm_150, 02h;
    Where:
    zmm_dst is the destination operand.
    zmm_src is the input operand to compare against ±150.
    zmm_150 is the reference operand, contains the value of 150.
    IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
    In case |zmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in zmm_dst
    will get the value of 150 (received on zmm_150).
    However, the sign control (imm8[3:2]=’00) instructs to select the sign of SRC1 received from zmm_src. So, even
    in the case of |zmm_src| ≥ 150, the selected sign of SRC1 is kept.
    Thus, if zmm_src < -150, the result of VRANGEPS will be the minimal value of -150 while if zmm_src > +150,
    the result of VRANGE will be the maximal value of +150.

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VRANGEPS __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);

    VRANGEPS __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);

    VRANGEPS __m512 _mm512_mask_range_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);

    VRANGEPS __m512 _mm512_mask_range_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm, int sae);

    VRANGEPS __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);

    VRANGEPS __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);

    VRANGEPS __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);

    VRANGEPS __m256 _mm256_mask_range_ps (__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);

    VRANGEPS __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);

    VRANGEPS __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);

    VRANGEPS __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);

    VRANGEPS __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);

### SIMD Floating-Point Exceptions ¶

Invalid, Denormal

### Other Exceptions ¶

See Table 2-46, “Type E2 Class Exception Conditions.”