# VCVTSD2USI — Convert Scalar Double Precision Floating-Point Value to Unsigned DoublewordInteger

Opcode/Instruction | Op/En | 64/32 Bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
EVEX.LLIG.F2.0F.W0 79 /r VCVTSD2USI r32, xmm1/m64{er} | A | V/V | AVX512F | Convert one double precision floating-point value from xmm1/m64 to one unsigned doubleword integer r32.
EVEX.LLIG.F2.0F.W1 79 /r VCVTSD2USI r64, xmm1/m64{er} | A | V/N.E.1 | AVX512F | Convert one double precision floating-point value from xmm1/m64 to one unsigned quadword integer zero-extended into r64.

> 1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.

## Instruction Operand Encoding ¶

Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Tuple1 Fixed | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

### Description ¶

Converts a double precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double precision floating-point value is contained in the low quadword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

### Operation ¶

#### VCVTSD2USI (EVEX Encoded Version) ¶

    IF (SRC *is register*) AND (EVEX.b = 1)
        THEN
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
        ELSE
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
    FI;
    IF 64-Bit Mode and OperandSize = 64
        THEN DEST[63:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
        ELSE DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
    FI

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);

    VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);

    VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);

    VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);

### SIMD Floating-Point Exceptions ¶

Invalid, Precision.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”