# VCVTUQQ2PD — Convert Packed Unsigned Quadword Integers to Packed Double PrecisionFloating-Point Values

Opcode/Instruction | Op/En | 64/32 Bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
EVEX.128.F3.0F.W1 7A /r VCVTUQQ2PD xmm1 {k1}{z}, xmm2/m128/m64bcst | A | V/V | AVX512VL AVX512DQ | Convert two packed unsigned quadword integers from xmm2/m128/m64bcst to two packed double precision floating-point values in xmm1 with writemask k1.
EVEX.256.F3.0F.W1 7A /r VCVTUQQ2PD ymm1 {k1}{z}, ymm2/m256/m64bcst | A | V/V | AVX512VL AVX512DQ | Convert four packed unsigned quadword integers from ymm2/m256/m64bcst to packed double precision floating-point values in ymm1 with writemask k1.
EVEX.512.F3.0F.W1 7A /r VCVTUQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er} | A | V/V | AVX512DQ | Convert eight packed unsigned quadword integers from zmm2/m512/m64bcst to eight packed double precision floating-point values in zmm1 with writemask k1.

## Instruction Operand Encoding ¶

Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A

### Description ¶

Converts packed unsigned quadword integers in the source operand (second operand) to packed double precision floating-point values in the destination operand (first operand).

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

### Operation ¶

#### VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Register ¶

    (KL, VL) = (2, 128), (4, 256), (8, 512)
    IF (VL == 512) AND (EVEX.b == 1)
        THEN
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
        ELSE
            SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
    FI;
    FOR j := 0 TO KL-1
        i := j * 64
        IF k1[j] OR *no writemask*
            THEN DEST[i+63:i] :=
                Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
            ELSE
                IF *merging-masking* ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE ; zeroing-masking
                        DEST[i+63:i] := 0
                FI
        FI;
    ENDFOR
    DEST[MAXVL-1:VL] := 0

#### VCVTUQQ2PD (EVEX Encoded Version) When SRC Operand is a Memory Source ¶

    (KL, VL) = (2, 128), (4, 256), (8, 512)
    FOR j := 0 TO KL-1
        i := j * 64
        IF k1[j] OR *no writemask*
            THEN
                IF (EVEX.b == 1)
                    THEN
                        DEST[i+63:i] :=
                Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
                    ELSE
                        DEST[i+63:i] :=
                Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
                FI;
            ELSE
                IF *merging-masking* ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE ; zeroing-masking
                        DEST[i+63:i] := 0
                FI
        FI;
    ENDFOR
    DEST[MAXVL-1:VL] := 0

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);

    VCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);

    VCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);

    VCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);

    VCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);

    VCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);

    VCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);

    VCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);

    VCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);

    VCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);

    VCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);

    VCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);

### SIMD Floating-Point Exceptions ¶

Precision.

### Other Exceptions ¶

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

Additionally:

#UD | If EVEX.vvvv != 1111B.