# VP2INTERSECTD/VP2INTERSECTQ — Compute Intersection Between DWORDS/QUADWORDS to aPair of Mask Registers

Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description
--- | --- | --- | --- | ---
EVEX.NDS.128.F2.0F38.W0 68 /r VP2INTERSECTD k1+1, xmm2, xmm3/m128/m32bcst | A | V/V | AVX512VL AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between dwords in xmm3/m128/m32bcst and xmm2.
EVEX.NDS.256.F2.0F38.W0 68 /r VP2INTERSECTD k1+1, ymm2, ymm3/m256/m32bcst | A | V/V | AVX512VL AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between dwords in ymm3/m256/m32bcst and ymm2.
EVEX.NDS.512.F2.0F38.W0 68 /r VP2INTERSECTD k1+1, zmm2, zmm3/m512/m32bcst | A | V/V | AVX512F AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between dwords in zmm3/m512/m32bcst and zmm2.
EVEX.NDS.128.F2.0F38.W1 68 /r VP2INTERSECTQ k1+1, xmm2, xmm3/m128/m64bcst | A | V/V | AVX512VL AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between quadwords in xmm3/m128/m64bcst and xmm2.
EVEX.NDS.256.F2.0F38.W1 68 /r VP2INTERSECTQ k1+1, ymm2, ymm3/m256/m64bcst | A | V/V | AVX512VL AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between quadwords in ymm3/m256/m64bcst and ymm2.
EVEX.NDS.512.F2.0F38.W1 68 /r VP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcst | A | V/V | AVX512F AVX512_VP2INTERSECT | Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between quadwords in zmm3/m512/m64bcst and zmm2.

## Instruction Operand Encoding ¶

Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4
--- | --- | --- | --- | --- | ---
A | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A

### Description ¶

This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.

EVEX.aaa and EVEX.z must be zero.

### Operation ¶

#### VP2INTERSECTD destmask, src1, src2 ¶

    (KL, VL) = (4, 128), (8, 256), (16, 512)
    // dest_mask_reg_id is the register id specified in the instruction for destmask
    dest_base := dest_mask_reg_id & ~1
    // maskregs[ ] is an array representing the mask registers
    maskregs[dest_base+0][MAX_KL-1:0] := 0
    maskregs[dest_base+1][MAX_KL-1:0] := 0
    FOR i := 0 to KL-1:
        FOR j := 0 to KL-1:
            match := (src1.dword[i] == src2.dword[j])
            maskregs[dest_base+0].bit[i] |= match
            maskregs[dest_base+1].bit[j] |= match

#### VP2INTERSECTQ destmask, src1, src2 ¶

    (KL, VL) = (2, 128), (4, 256), (8, 512)
    // dest_mask_reg_id is the register id specified in the instruction for destmask
    dest_base := dest_mask_reg_id & ~1
    // maskregs[ ] is an array representing the mask registers
    maskregs[dest_base+0][MAX_KL-1:0] := 0
    maskregs[dest_base+1][MAX_KL-1:0] := 0
    FOR i = 0 to KL-1:
        FOR j = 0 to KL-1:
            match := (src1.qword[i] == src2.qword[j])
            maskregs[dest_base+0].bit[i] |= match
            maskregs[dest_base+1].bit[j] |= match

### Intel C/C++ Compiler Intrinsic Equivalent ¶

    VP2INTERSECTD void _mm_2intersect_epi32(__m128i, __m128i, __mmask8 *, __mmask8 *);

    VP2INTERSECTD void _mm256_2intersect_epi32(__m256i, __m256i, __mmask8 *, __mmask8 *);

    VP2INTERSECTD void _mm512_2intersect_epi32(__m512i, __m512i, __mmask16 *, __mmask16 *);

    VP2INTERSECTQ void _mm_2intersect_epi64(__m128i, __m128i, __mmask8 *, __mmask8 *);

    VP2INTERSECTQ void _mm256_2intersect_epi64(__m256i, __m256i, __mmask8 *, __mmask8 *);

    VP2INTERSECTQ void _mm512_2intersect_epi64(__m512i, __m512i, __mmask8 *, __mmask8 *);

### SIMD Floating-Point Exceptions ¶

None.

### Other Exceptions ¶

See Table 2-50, “Type E4NF Class Exception Conditions.”